A couple of papers at last week’s ISSCC (the IEEE International Solid-State Circuits Conference) caught The Memory Guy’s attention. Both SK hynix and Samsung showed low-power DRAM designs in which the refresh rate of the DRAM was reduced in order to cut power consumption, with ECC applied to correct the resulting bit errors.
Although I had not heard of this approach before, I have recently learned that researchers at Carnegie Mellon University and my alma mater Georgia Tech presented the idea in a paper delivered at another IEEE conference in 2015: The International Conference on Dependable Systems and Networks.
Here’s the basic concept: DRAM consumes most of its power performing refresh cycles, the issue for which it was given the “Dynamic” part of its name: Dynamic Random-Access Memory. This use of the word “Dynamic” is a euphemism. In reality the bits are constantly decaying, but that doesn’t sound as nice.
When the technology was developed in the early 1970s DRAM manufacturers offered to Continue reading
At the International Solid State Circuits Conference (ISSCC) last week a new “Last Level Cache” was introduced by a DRAM company called “Piecemakers Technology,” along with Taiwan’s ITRI, and Intel.
The chip was designed with a focus on latency, rather than bandwidth. This is unusual for a DRAM.
Presenter Tah-Kang Joseph Ting explained that, although successive generations of DDR interfaces has increased DRAM sequential bandwidth by a couple of orders of magnitude, latency has been stuck at 30ns, and it hasn’t improved with the WideIO interface or the new TSV-based High Bandwidth Memory (HBM) or the Hybrid Memory Cube (HMC). Furthermore, there’s a much larger latency gap between the processor’s internal Level 3 cache and the system DRAM than there is between any adjacent cache levels. The researchers decided to design a product to fill this gap.
This week both the Toshiba-Western Digital team and Samsung disclosed details of their 64-layer 3D NAND designs at the IEEE’s International Solid-State Circuits Conference (ISSCC). The Memory Guy thought that it would be interesting to compare these two companies’ 64-layer chips against each other and against the one that Micron presented at last year’s ISSCC.
Allow me to point out that it’s no easy feat to get to 64 layers. Not only must the process build all 64 layers (or actually pairs of layers plus some additional ones for control) across the entire 300mm wafer with high uniformity and no defects, but then holes must be etched through varying materials from the top to the bottom with absolutely parallel sides at aspect ratios of about 60:1, that is, the hole is 60 times as deep as it is wide. After this the fab must deposit uniform layers of material onto the sides of these skinny holes without any variation in thickness.
None of these processes have ever been used to build any other semiconductor — it’s all brand new. This is what makes 3D NAND so challenging, and it’s why the technology is already 3 years behind its original schedule.
It’s not easy to tell from the conference papers whether or not Continue reading
In a letter to shareholders released today, Toshiba finally clarified its plans for restructuring the company. Since January 18 there have been numerous rumors that Toshiba planned to spin its memory business off or sell it outright. Today’s letter indicates that this hasn’t been decided yet. In fact, other than to call a late March shareholder vote and to reveal a restructuring, the letter discloses extraordinarily little.
In a nutshell Toshiba has decided to isolate the memory business (including the SSD business but not the HDD and image sensor businesses) into a separate wholly-owned subsidiary. There was no mention of either the recently-shrinking Discrete business or the System LSI business, which has been in a steady decline for the past decade. Click on this post’s graphic to see how each of the company’s semiconductor businesses has been doing.
The intent appears to be to groom the subsidiary to be spun off or sold, but this has not been expressly stated. Instead Toshiba simply states that: “The Company is still considering various structures with a view to an injection of third-party capital.”
The letter reiterates Toshiba’s prior position that the memory business Continue reading
On its way out the door the Obama Administration put together a proposed response to China’s plans to invest $150 billion in the semiconductor market over the next five years. It seems that US semiconductor industry views China’s investment as a threat to its position in the market.
Last week the President’s Council of Advisors on Science and Technology (PCAST) delivered a 25-page Report to the President entitled: “Ensuring Long-Term U.S. Leadership in Semiconductors.”
You might ask: “Who is PCAST?” The organization states its mission in this paragraph: “The President’s Council of Advisors on Science and Technology (PCAST) is an advisory group of the Nation’s leading scientists and engineers, appointed by the President to augment the science and technology advice available to him from inside the White House and from cabinet departments and other Federal agencies. PCAST is consulted about, and often makes policy recommendations concerning, the full range of issues where understandings from the domains of science, technology, and innovation bear potentially on the policy choices before the President.”
PCAST has a small Semiconductors Working Group whose elite members include Continue reading
Since I am the Memory Guy I hate learning that I missed something new and cool in the world of memories, but somehow I was unaware of last week’s Memsys conference in Washington DC until a participant notified me on Saturday that his paper: “Reverse Engineering of DRAMs: Row Hammer with Crosshair,” had been given the the best paper award.
Upon looking at the Memsys website it looks like a very intriguing academic conference. about sixty papers were presented in eight interesting sessions:
- Issues in High Performance Computing
- Nonvolatile Main Memories and DRAM Caches, Parts I & II
- Hybrid Memory Cube and Alternative DRAM Channels
- Thinking Outside the Box
- Improving the DRAM Device Architecture
- Issues and Interconnects for 2.5D and 3D Packaging
- Some Amazingly Cool Physical Experiments
in addition to a few apparently-fascinating keynotes.
Fortunately, all of the papers are Continue reading
After a big 3D XPoint launch one year ago almost anyone would expect for Intel to have had a lot of exciting new news to share about the technology at last week’s Intel Developer Forum (IDF). Those who were watching for that, though, were in for a disappointment.
For readers who don’t remember, Intel and its partner, chipmaker Micron Technology, announced a new memory layer in July 2015 that would enable in-memory databases to expand well beyond the constraints posed by standard DRAM memory. The pair also boasted the additional benefit of being nonvolatile or persistent – data would not be lost if the power failed. This technology promised to open new horizons in the world of computing.
Intel devoted a lot of effort to promotion and education during the following month’s IDF, and even demonstrated a prototype 3D XPoint SSD that performed seven to eight times as fast as Intel’s highest-performance existing NAND flash SSD – the DC S3700. Although a DIMM form factor was disclosed, no prototypes were on hand. Both were given the brand name “Optane”.
The Memory Guy has been getting calls lately asking how to tell that a shortage is developing. My answer is always the same: It’s hard to tell.
One indicator is that spot prices which were below contract prices rise above contract prices. This doesn’t happen for all components or densities of DRAM or NAND flash at the same time. Some of these transitions are temporary as well. It takes patience to see if it was a momentary change or if it was the onset of a shortage.
DRAM spot prices have generally been below contract prices since August 2014, but this month they raised above contract prices. NAND flash spot prices also fell below contract prices in mid-2014 but today NAND’s spot price remains lower than contract prices.
Lead times represent another indicator. If the lead time for a number of components increases then those chips are moving into a shortage. Lead times have recently been rising for both NAND flash and DRAM.
A third indication occurs when suppliers start to Continue reading
According to a Business Korea article Samsung announced, during a June 14 investor event, plans to reduce its DRAM capital spending and shift its focus to 3D NAND.
The Memory Guy sees this as an unsurprising move. This post’s chart is an estimate of DRAM wafer production from 1991 through 2014. There is a definite downtrend over the past few years. The peak was reached in 2008 at an annual production of slightly below 15 million wafers, with a subsequent dip in 2009 thanks to the global financial collapse at the end of 2008. After a slight recovery in 2010 the industry entered a period of steady decline.
The industry already has more than enough DRAM wafer capacity for the foreseeable future.
Why is this happening? The answer is relatively simple: the gigabytes per wafer on a DRAM wafer are growing faster than the market’s demand for gigabytes.
Let’s dive into that in more detail. The number of gigabytes on a DRAM wafer increases according Continue reading
The answer really depends upon who you ask. An article in the Financial Express quoted Samsung as saying that it would have a minimal impact, and that full-scale operations should resume in a few days. The article also said that Samsung estimated that the wafer loss would be below 10,000 wafers.
Assuming that the entire loss consisted of Samsung’s most advanced 48-layer 256Gb 3D NAND a 10,000-wafer loss would be less than 1% of total industry gigabyte shipments.
Korea Times quoted an anonymous fund manager who said: “The one-time incident will cost Samsung up to 20 billion won, which is very minimal. It won’t make heavy impact on Samsung’s chip business and the entire industry.”