After a big 3D XPoint launch one year ago almost anyone would expect for Intel to have had a lot of exciting new news to share about the technology at last week’s Intel Developer Forum (IDF). Those who were watching for that, though, were in for a disappointment.
For readers who don’t remember, Intel and its partner, chipmaker Micron Technology, announced a new memory layer in July 2015 that would enable in-memory databases to expand well beyond the constraints posed by standard DRAM memory. The pair also boasted the additional benefit of being nonvolatile or persistent – data would not be lost if the power failed. This technology promised to open new horizons in the world of computing.
Intel devoted a lot of effort to promotion and education during the following month’s IDF, and even demonstrated a prototype 3D XPoint SSD that performed seven to eight times as fast as Intel’s highest-performance existing NAND flash SSD – the DC S3700. Although a DIMM form factor was disclosed, no prototypes were on hand. Both were given the brand name “Optane”.
The Memory Guy has been getting calls lately asking how to tell that a shortage is developing. My answer is always the same: It’s hard to tell.
One indicator is that spot prices which were below contract prices rise above contract prices. This doesn’t happen for all components or densities of DRAM or NAND flash at the same time. Some of these transitions are temporary as well. It takes patience to see if it was a momentary change or if it was the onset of a shortage.
DRAM spot prices have generally been below contract prices since August 2014, but this month they raised above contract prices. NAND flash spot prices also fell below contract prices in mid-2014 but today NAND’s spot price remains lower than contract prices.
Lead times represent another indicator. If the lead time for a number of components increases then those chips are moving into a shortage. Lead times have recently been rising for both NAND flash and DRAM.
A third indication occurs when suppliers start to Continue reading
According to a Business Korea article Samsung announced, during a June 14 investor event, plans to reduce its DRAM capital spending and shift its focus to 3D NAND.
The Memory Guy sees this as an unsurprising move. This post’s chart is an estimate of DRAM wafer production from 1991 through 2014. There is a definite downtrend over the past few years. The peak was reached in 2008 at an annual production of slightly below 15 million wafers, with a subsequent dip in 2009 thanks to the global financial collapse at the end of 2008. After a slight recovery in 2010 the industry entered a period of steady decline.
The industry already has more than enough DRAM wafer capacity for the foreseeable future.
Why is this happening? The answer is relatively simple: the gigabytes per wafer on a DRAM wafer are growing faster than the market’s demand for gigabytes.
Let’s dive into that in more detail. The number of gigabytes on a DRAM wafer increases according Continue reading
The answer really depends upon who you ask. An article in the Financial Express quoted Samsung as saying that it would have a minimal impact, and that full-scale operations should resume in a few days. The article also said that Samsung estimated that the wafer loss would be below 10,000 wafers.
Assuming that the entire loss consisted of Samsung’s most advanced 48-layer 256Gb 3D NAND a 10,000-wafer loss would be less than 1% of total industry gigabyte shipments.
Korea Times quoted an anonymous fund manager who said: “The one-time incident will cost Samsung up to 20 billion won, which is very minimal. It won’t make heavy impact on Samsung’s chip business and the entire industry.”
At a technical conference hosted by the IEEE this week IBM announced the results of nearly a decade of research in which its scientists have been investigating the emerging technology known as “Phase Change Memory” (PCM). The scientists presented a means of successfully storing three bits per cell for the first time, while also addressing all of PCM’s challenging idiosyncrasies, including resistance drift and temperature drift.
Commonly referred to by the erroneous nickname “TLC” for Triple Level Cell, this technology squeezes three bits of data into the space of a single bit, essentially cutting the cost per gigabyte to about one third of that of a standard memory chip making it closer in cost to flash.
With this step IBM expects to help drive a new memory layer into existence, one that will fit between the cheap and slow NAND flash used in SSDs and the fast but expensive DRAM used for main memory. Such a layer would improve the cost/performance of all types of Continue reading
For almost two years there has been a lot of worry about DRAM spot prices. This post’s graphic plots the lowest weekly spot price per gigabyte for the cheapest DRAM, regardless of density, on a semi-logarithmic scale. (Remember that on a semi-logarithmic scale constant growth appears as a straight line.)
The downward-sloping red line on right side of the chart shows that DRAM prices have been sliding at a 45% annual rate since October 2014. This has a lot of people worried for the health of the industry.
What most fail to remember, though, is that DRAM spot prices hit their lowest point twice in 2011, at $2.40 in August, and then $2.20 in November. Today’s lowest DRAM spot prices have only recently dipped below the $2.52 point hit in October of 2014.
The black dotted line in the chart is intended to focus readers’ attention on DRAM costs, which decrease at a 30% average Continue reading
One of those nasty little secrets about DRAM is that bits may get corrupted by simply reading the bits in a different part of the chip. This has been given the name “Row Hammer” (or Rowhammer) because repeated accesses to a single one of the DRAM’s internal “rows” of bits can bleed charge off of the adjacent rows, causing bits to flip. These repeated accesses are referred to as “hammering”.
Although this was once thought to be an issue only with DDR3 DRAMs, recent papers (listed on the DDR Detective) show that DDR4 also suffers from Row Hammer issues, even though DRAM makers took pains to prevent it.
One big champion of this phenomenon is Barbara Aichinger (pictured) of FuturePlus Systems, a test equipment maker that specializes in detecting row hammer issues. The Memory Guy has had the pleasure of talking with her about this issue and learning first-hand the kind of difficulties it creates.
How does Row Hammer work? It stems from the fact Continue reading
China foundry XMC has broken ground for its new 3D NAND flash fab, the country’s first China-owned 3D NAND flash facility. Plans for this fab were publicly disclosed over a year ago. Simon Yang, XMC’s CEO, gave a presentation at SEMI’s Industry Strategy Symposium (ISS) on January 11, 2015 in which he detailed the need for China to produce a larger proportion of its overall chips, explaining how his company would help make that happen.
Yang used the map in this post’s graphic to show that XMC has enough land on its campus for six 300mm wafer fabs. Two shells (yellow), each capable of processing 30,000 wafers per month, had been constructed by that time: Fab A (left) was already fully utilized, and Fab B (right) was ready for tooling. The gray boxes show that the site has enough space to build 2 additional 2-line megafabs, each with a capacity of up to 100k wafers per month. Accoding to DRAMeXchange XMC currently produces 20,000 wafers of NOR flash per month. A March 30 China Daily article reports that monthly wafer production will reach 300,000 in 2020 and 1 million in 2030.
XMC’s formal name is Wuhan Xinxin Semiconductor Manufacturing, and it is located Continue reading
Beleaguered Toshiba finally unveiled its restructuring plan on Friday. The plan aims to return the company to profitability and growth through management accountability.
A lot of the presentation focused on the memory business, a shining star of the Toshiba conglomerate, which has so far included appliances, nuclear power plants, and medical electronics.
Toshiba has big plans for its Semiconductor & Storage Products Company, calling it “A pillar of income with Memories as a core business”. The company plans to enhance its NAND flash cost competitiveness by accelerating development of BiCS (Toshiba’s 3D NAND technology) and by expanding its SSD business. There are three parts to this effort:
- Grow 3D NAND production capacity
- Speed up 3D NAND development
- Increase SSD development resources
This post’s graphic is an Continue reading
It was sad to hear today of the passing of Andy Grove, Intel co-founder and former president.
Although I did not know him well, Andy was a part of my brief 1½-year stint at Intel in the early 1980s. He played a key role in my “IOPEC” new employee training, and he and I were in cubicles on the same floor of the same Intel office building, so we would run into each other from time to time during the business day.
Plenty has been said about this man’s competence as a manager, and plenty more will be said. He drove the creation of the world’s leading semiconductor manufacturer.
I think I was most impressed, though, when he agreed to be interviewed for a PBS television special on the history of the semiconductor industry: “Silicon Valley: American Experience” despite the fact that his battle with Parkinson’s Disease had already rendered it difficult for him to speak.
I always meant to write to him to tell him how impressed I was that he would do that. I guess I won’t have the chance now.