Objective Analysis has just introduced a new report that you might want to consider: A Close Look At The Micron/Intel 3D XPoint Memory.
The report covers the Intel-Micron 3D XPoint memory and includes Intel’s new Optane support products that are based on this technology. The report explains the technology and its special manufacturing challenges. It includes details of how 3D XPoint memory will be used, and provides an analysis of the benefits of its persistent nature.
Forecasts project how the market will develop and include optimistic and pessimistic forecast scenarios. Particular attention has been paid to its impact upon the DRAM, SSD, and other markets. Finally, the report analyzes different end-market segments to predict how this technology will impact each of them.
The Memory Guy, report author Jim Handy, will present the report’s findings during the Pre-Conference Primer of the Storage Network Industry Association (SNIA) Storage Developer Conference (SDC) this Sunday, September 20, at 2:00 PM, In Santa Clara, CA.
This breakthrough report is based on Continue reading
For years SanDisk has been presenting a memory roadmap (this post’s graphic is one rendition) that anticipates a move to ReRAM after 3D NAND has run through its natural life, which was expected to be as little as three generations. This has been backed by the idea that a 3D NAND stack would only be able to reach a certain number of layers before it would encounter difficulties caused by the need to etch a high aspect ratio hole through an increasing number of layers.
The aspect ratio issue is not hard to understand: Let’s assume that the hole in a 24-layer stack has an aspect ratio of 40:1, then a 32-layer hole would have an aspect ratio of about 50:1, and a 64-layer stack would be something close to 100:1. Today’s technology starts to have trouble etching holes with an aspect ratio higher than 60:1.
These high aspect ratios were thought to be the limiting factor that would prevent 3D NAND from continuing for more than three generations. 3D NAND could only have as many layers as the aspect ratio could support.
On a panel that I moderated at this year’s Flash Memory Summit one panelist, Dr. Myoung Kwan Cho of SK hynix, explained that although there is a limit Continue reading
How short is that list? Interestingly, Intel and Micron have different lists. The Micron list, shown in this post’s graphic (click to enlarge), cites seven types: “Ram” (showing a vacuum tube), PROM, SRAM, DRAM, EPROM, NOR flash, and NAND flash. Intel’s list adds magnetic bubble memory, making it eight. (Definitions of these names appear in another Memory Guy blog post.)
The Memory Guy finds both lists puzzling in that they left out a number of important technologies.
For example, why did Intel neglect EEPROM, which was an Intel invention that is still in widespread use? EEPROMs (or E²PROMs) are not only found in nearly every application that has a serial number (ranging from WiFi routers to credit cards), requires calibration (like blood glucose monitoring strips and printer ink cartridges), or provides operating parameters (i.e. the serial presence detect – SPD – in DRAM DIMMs), but they still ship in the billions of units every year. In its time EEPROM was an important breakthrough. Over the years EEPROM has had a much greater impact than has PROM.
And, given that both companies were willing to include tubes, a non-semiconductor technology, why did both Continue reading
Micron and Intel hosted an event in San Francisco Tuesday, July 28, to introduce a new memory technology that they have named “3D XPoint”. This technology was explained to be “up to 1,000 times faster, with 1,000 times the endurance of NAND flash” while being significantly cheaper than DRAM.
Some technical details:
- 3D XPoint is a “Fundamentally Different Technology” than current memory types. It’s an ReRAM that uses material property changes for bit storage where both DRAM and NAND use charge to store a bit
- The chip currently stores 128Gb in two stacked planes of 64Gb each, storing a single bit per cell
- Today’s densest production NAND flash chips store 128GB by using MLC, so this chip actually has twice as many bit cells as any production NAND flash
- The companies do not see a clear limit to the number of planes they can stack, but are optimistic about this
- The bulk mechanism can be used to store multiple bits on a single cell (MLC)
- Today’s chip is made using a 20nm process, but can scale well past that
- There is no clear limit of how far the technology can be scaled
- It’s 1,000 times faster than NAND flash and offers 1,000 times NAND’s endurance
- It’s 10 times as dense as today’s “Conventional Memory” (which I suppose to be DRAM)
- This is not intended to replace either NAND or DRAM, but to coexist as a new memory layer between NAND and DRAM
The companies claim that other Continue reading
A July 13 Wall Street Journal article disclosed that China’s state-owned Tsinghua Unigroup has bid to buy Micron Technology for $21 a share or $23 billion, which would make this the largest-ever Chinese takeover of a U.S. company.
Objective Analysis has been telling our clients for the past few years that either China or India would create a new DRAM/NAND manufacturing company, especially since memory chip makers have enjoyed a long period of profits, and this usually motivates outsiders to invest in new DRAM makers. We did not anticipate an acquisition.
Countries with heavy industry typically move into the semiconductor business during an extended upturn, and become DRAM suppliers since DRAM is an undifferentiated commodity. Commodities sell almost solely on price and success is based on little more than manufacturing strength. This is a business model that industrial economies understand.
In addition to Micron’s tangible assets, including Continue reading
Today Avalanche Technology announced that it is sampling MRAM, making it the world’s second company to actually produce this much-researched technology.
For those unfamiliar with MRAM, it is one of a number of technologies being positioned to replace currently-entrenched memory technologies once they reach their scaling limits. Regular Memory Guy readers know that this juncture has been anticipated for a few decades, but always seems to get postponed.
MRAM, like many other alternative technologies, offers the promise of scaling beyond the limits of DRAM and NAND to become cheaper than ether of these technologies. Add to this its fast write speed, low power, lack of refresh, nearly unlimited endurance, and nonvolatility, and it becomes a very compelling alternative over the long term.
As opposed to the other MRAM-maker Everspin, Avalanche’s MRAM uses Continue reading
In a comment to a recent Memory Guy post I stated that NAND flash can reduce DRAM requirements, even in PCs. Some readers have told me that they wonder how this could be, so I will write this post to explain.
Some years ago Objective Analysis noticed that clever server administrators were able to use SSDs to reduce their systems’ DRAM requirements. Not only did this save them money, but it lowered power and cooling requirements as well.
Thinking that this might work on other kinds of computers, we commissioned a number of benchmarks to be performed on a PC.
These benchmarks found that after a system already has a certain minimum amount of DRAM, users can get a bigger performance boost by adding a dollar’s worth NAND flash than they can get by adding a dollar’s worth of DRAM.
In every case the minimum amount of DRAM was very small.
There has been quite a lot of interest over the past few days about the apparently-inadvertent disclosure by Intel of its server platform roadmap. Detailed coverage in The Platform showed a couple of slides with key memory information for the upcoming Purley server platform which will support the Xeon “Skylake” processor family.
One slide, titled: “Purley: Biggest Platform Advancement Since Nehalem” includes this post’s graphic, which tells of a memory with: “Up to 4x the capacity & lower cost than DRAM, and 500x faster than NAND.”
The Memory Guy puzzled a bit about what this might be. The only memory chip technology today with a cost structure lower than that of DRAM is NAND flash, and there is unlikely to be any technology within the leaked roadmap’s 2015-2017 time span that will change that. MRAM, ReRAM, PCM, FRAM, and other technologies can’t beat DRAM’s cost, and will probably take close to a decade to get to that point.
Since that’s the case, then what is this mystery memory? If we think of memory systems, rather than memory chips we can come up with one very plausible answer. Intel may be very Continue reading
Today’s low spot price of $4.30/GB puts us on a par with February 2013, a full two years ago (see chart). DRAM makers have done a lot to reduce their production costs since that time, so their margins this quarter will be much better than they were in the first quarter of 2013.
But we are still a very long way from the bottom of the last market downturn. In late 2012 spot prices reached a low of $2.52/GB, a full 41% lower than today’s lowest spot prices.
The Memory Guy models the production costs of leading memory chips, and DRAM manufacturing costs have been decreasing for the past several years at an average annual rate of about 30%. That means that costs today are about half of what they were two years ago, and one third of their level this time in 2012.
So even though today’s Continue reading
A lone inventor has developed a data compression algorithm that defies the theoretical “Shannon Limit“. The press hasn’t covered this recent news, even though it has dramatic implications. This is probably because the technique is so very arcane. The inventor is none other than the great-great-great granddaughter of the inventor of the tabulated punch card, Herman Hollerith.
The algorithm reduces most of the data while converting the remaining information into as many ones as possible. This not only shrinks storage requirements and costs, but in the case of flash memory, it also has an important impact on total power. Flash is erased by setting all bits to ones, and bits are written by either leaving them alone (one) or by changing them (zero). The fewer zeros in the code, the less energy required to change the bits. Energy is also saved during an erase, since fewer bits need to be brought back to the erased state.
To explain the algorithm in its simplest terms, a byte of data is evaluated. If it has more zero bits than one bits the byte is inverted and an index bit is set to reflect this fact. Next, the four bits on either side of the byte are evaluated and if one has more zeros than ones it is inverted and another index bit is set. This process continues until Continue reading