Micron’s Super-Fast New 32GB NVDIMM


Switch TrackMicron Technology has introduced a 32GB NVDIMM-N.  Perhaps the most important thing about this device is not so much its high density as the fact that it runs at higher bus speeds than competing NVDIMMs, doing 2933 megatransfers per second (MT/s), a speed that Micron representatives tell us is required to support Intel’s Skylake processor.

Up to this point NVDIMM-Ns have been limited to 2400 MT/s, which is fast enough for Broadwell, but which misses the mark for Skylake.  Design is tricky even at this slower speed, requiring a number of expensive high-speed multiplexers in the DRAM’s critical speed path.

“Multiplexers?”  Yes, NVDIMMs use them, even though no other kind of DIMM does.  The Memory Guy can explain why, having just finished a report covering the NVDIMM market and technology.

Here’s a little refresher for those who either don’t remember or never knew that NVDIMM-N requires multiplexers.  The NVDIMM-N looks to the system like a standard Continue reading

New Report Details NVDIMM Market

Objective Analysis NVDIMM Report 2017 CoverObjective Analysis has just released a new report covering the nonvolatile dual inline memory module (NVDIMM) market in detail.  This report, Profiting from the NVDIMM Market, explains the What, How, Why, & When of today’s and tomorrow’s NVDIMM products.

My readers know that I have been watching this market for some time, and that I am always perplexed as to whether to post about NVDIMMs in The Memory Guy or in The SSD Guy, since these products straddle the boundary between memory and storage.  This time my solution is to publish posts in both!

The Objective Analysis NVDIMM market model reveals that the market for NVDIMMs is poised to grow at a 105% average annual rate to nearly 12 million units by 2021.  This finding is based on a forecast methodology that has provided many of the most consistently-accurate forecasts in the semiconductor business.  This forecast, and the report itself, were compiled through exhaustive research into the technology and the events leading up to its introduction, vendor and user interviews, and briefings from standards bodies.

This 80-page in-depth analysis examines all leading NVDIMM types and forecasts their unit and revenue shipments through 2021.  Its 42 figures and 14 tables help Continue reading

Did Toshiba REALLY Lose 3-6 Weeks’ Production?

Toshiba's Fab 5 in YokkaichiYesterday The Memory Guy learned of an amazing article in DigiTimes about a 3-6 week shutdown at Toshiba’s Yokkaichi NAND flash fab line.  According to the story Toshiba’s production was shut down for 3-6 weeks accounting for a production loss of 100,000 wafers.  Another article in PC Games N converted that to lost bytes and came up with the number 400,000 terabytes.

Some quick math shows the errors in both of these articles.

First of all, the wafer stoppage.  The Toshiba/SanDisk Yokkaichi Joint Venture wafer fabrication complex processes a little over 2 million wafers per year.  Divide that by 52 weeks and you find that’s about 40,000 wafers per week, so 100,000 wafers would be 2.5 weeks’ output, not 3-6 weeks.

The number of bytes that PC Games N published takes a little more math.  According to TechInsights Toshiba’s 15nm 128Gb MLC chip has an area of 99mm².  That gets you a little over 10TB/wafer.  The company’s 48-layer TLC 256Gb part should produce about twice that.  Yet, if you divide PC Games’ Continue reading

How Samsung Will Improve 3D NAND Costs

Samsung's New Stairstep Etch iOne of the most intriguing revelations during the Flash Memory Summit two weeks ago was Samsung’s new approach to stairstep etch in 3D NAND.  This was one of numerous innovations the company’s  EVP of Flash Products & Technologies, Kye Hyun (KH) Kyung, shared during Samsung’s Tuesday Morning keynote presentation.

The Memory Guy would point readers to the pdf of Samsung’s presentation on the Flash Memory Summit website, but it isn’t there, and it’s unlikely to ever be posted there.  Samsung seems to have a policy that prohibits sharing such presentations.

Although I was unable to get a copy of the drawing that the keynoter used, I have tried to re-create it using, of all things, Excel!  The result is the graphic for this blog post.  The only thing I was unable to easily recreate was the different colors representing the layers of the 3D NAND.  You’ll need to use your imagination and envision layers of two colors, with all the surfaces exposed on the top being the same color, but at different layers of a 64-layer structure.

Today’s common approach to 3D NAND’s stairstep is to etch a simple step pattern in one dimension, which I illustrated in an early 3D NAND blog post four years ago.  This is a challenging Continue reading

3D NAND: “I Have More Layers than You Do!”

Layer CountYesterday’s news really underscored the race currently underway between 3D NAND makers to produce higher layer counts than one another.

Intel produced an announcement in which VP Rob Crooke bragged that: “Intel has delivered the world’s first commercially available 64-layer, TLC, 3D NAND solid state drive (SSD). While others have been talking about it, we have delivered.”

The announcement explained that the new Intel SSD 545s could be purchased at Newegg beginning that day.

The Memory Guy received Intel’s announcement at 10:02 AM Pacific Time.  By 3:11 PM, five hours later, there was another announcement in my “In” box, this time from Western Digital (WDC).

WDC’s e-mail announced the development of the the SanDisk/Toshiba next-generation BiCS4 3D NAND technology, with 96 layers.  The companies expect to begin to sample a 256Gb part to OEM customers in the second half of 2017 with production starting by the end of next year.

One has to wonder if WDC was Continue reading

Super-Cooled DRAM for Big Power Savings

Frozen DRAM - Hacker10Recently Rambus announced that it was using cryogenic temperatures to boost computer performance in large datacenters.  This research is being done in a joint project with Microsoft who is developing a processor based on Josephson Junctions.

This is an effort to provide a performance increases greater than can be attained through standard semiconductor scaling.  The research project aims to attain improvements in cycle time, power consumption, and compute density, leading to better energy efficiency and cost of ownership (COO).  The companies hope to gain side benefits of being able to squeeze more bits onto a DRAM chip thus reducing cost per bit, improving performance, and making DRAM chips less costly to produce.

The system these two companies are researching uses a memory system that is cooled to 77 degrees Kelvin (77°K) with a processor that operates at 4°K.  To do this the memory system is bathed in liquid nitrogen while the processor is cooled by liquid helium.  The temperatures are the boiling points of these two liquids.

Surprisingly, the fact that these two subsystems are in different Continue reading

Examining 3D XPoint’s 1,000 Times Endurance Benefit

3D XPoint Endurance GraphicThe Memory Guy, as a regular reader of The SSD Guy’s posts, found an interesting one that compares the endurance of Optane SSDs against that of NAND flash SSDs.  Perhaps this could provide some insight into the Intel & Micron claim that 3D XPoint Memory’s endurance is 1,000 times that of standard NAND flash, shown in the graphic to the left.

The SSD Guy post converts several different measures of SSD endurance against each other: TBW, DWPD, and GB/Day.  Definitions of these terms can be found in that post.

It occurred to me that any of these can be used to roughly gauge the relative endurance of 3D XPoint Memory against that of NAND flash.

Take DWPD for example: Drive Writes per Day.  Not only is this a measure of how many times that an SSD can be over-written every day, but it’s also an indication of the number of times that each memory cell can be overwritten.  If you know this, and if you know how long Continue reading

Why Satellites Are Programmed Differently

We Are Doomed!Most engineers never consider the weight of the firmware in their designs.  You probably are saying to yourself: “Firmware doesn’t weigh anything!”  In fact, you are wrong.

There is probably no application to which this is more important than the satellite industry.  With payloads costing $20 – $40 per gram to launch into Earth orbit the weight of firmware becomes an enormously important part of the cost of putting a satellite into orbit.

Amplify this by the fact that a growing number of hardware-based functions are being replaced by their firmware equivalents, and by the fact that modularized firmware is being used to replace smaller hand-tuned subroutines with larger general-purpose routines, and you find that the number of ones and zeros in the average satellite is ballooning at a rate of more than ten times per year.

Is this bad?  In this blog post The Memory Guy will put some numbers around the issue.

Firmware is stored as ones and zeros.  In flash memory or DRAM these ones and zeros are stored either by adding Continue reading

Using ECC to Reduce Power

CMU Most DRAM Refreshes UnnecessaryA couple of papers at last week’s ISSCC (the IEEE International Solid-State Circuits Conference) caught The Memory Guy’s attention.  Both SK hynix and Samsung showed low-power DRAM designs in which the refresh rate of the DRAM was reduced in order to cut power consumption, with ECC applied to correct the resulting bit errors.

Although I had not heard of this approach before, I have recently learned that researchers at Carnegie Mellon University and my alma mater Georgia Tech presented the idea in a paper delivered at another IEEE conference in 2015: The International Conference on Dependable Systems and Networks.

Here’s the basic concept: DRAM consumes most of its power performing refresh cycles, the issue for which it was given the “Dynamic” part of its name: Dynamic Random-Access Memory.  This use of the word “Dynamic” is a euphemism.  In reality the bits are constantly decaying, but that doesn’t sound as nice.

When the technology was developed in the early 1970s DRAM manufacturers offered to Continue reading

Is Intel Adding Yet Another Memory Layer?

Where the Piecemakers DRAM FitsAt the International Solid State Circuits Conference (ISSCC) last week a new “Last Level Cache” was introduced by a DRAM company called “Piecemakers Technology,” along with Taiwan’s ITRI, and Intel.

The chip was designed with a focus on latency, rather than bandwidth.  This is unusual for a DRAM.

Presenter Tah-Kang Joseph Ting explained that, although successive generations of DDR interfaces has increased DRAM sequential bandwidth by a couple of orders of magnitude, latency has been stuck at 30ns, and it hasn’t improved with the WideIO interface or the new TSV-based High Bandwidth Memory (HBM) or the Hybrid Memory Cube (HMC).  Furthermore, there’s a much larger latency gap between the processor’s internal Level 3 cache and the system DRAM than there is between any adjacent cache levels.  The researchers decided to design a product to fill this gap.

Many readers may be familiar with my bandwidth vs. cost chart that the Memory Guy has used to introduce SSDs and 3D XPoint memory.  The gap that needs filling is Continue reading


Jim Handy Objective Analysis Memory Market Research +1 (408) 356-2549 Jim.Handy (at) Objective-Analysis.com

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