Amazing 3D NAND Video

Carl Zeiss 3D NAND SEM videoChip reverse-engineering consultant Dick James pointed The Memory Guy to an absolutely amazing 25-second video of a 3D NAND chip.  The video’s made by the Carl Zeiss company.  It’s the second one from the top on this page: https://www.zeiss.com/semiconductor-manufacturing-technology/products-solutions/process-control-solutions/crossbeam-fib-sem.html

The video zooms around a portion of a 3D NAND die as layers are etched away and then restored.  Only the tungsten parts of the chip are shown, with the rest appearing to be empty space.  This serves to clarify it a good bit.  Dick James says that this makes it the equivalent of a 3D x-ray tomograph.

It’s a promotional piece for a Zeiss tool called the “Crossbeam FIB-SEM” that can both image and mill a chip.

Now I doubt that most Memory Guy readers would have a need for this tool, nor be able to afford something which is doubtlessly very expensive, but I am sure that anyone would admire what  it can do.  I certainly find it to be impressive!

Naturally, Dick James was able to identify the chip just by looking at it.  He says that it’s Samsung’s 32-layer part.

Original PCM Article from 1970

For a number of years The Memory Guy has wanted to find a copy of the 1970 article, published in Electronics magazine, in which Intel’s Gordon Moore and two authors from Energy Conversion Devices, Ron Neale and D.L. Nelson, showed that PCM could be used as a memory device.  After all, this is the technology behind Micron & Intel’s 3D XPoint Memory.

The cover of the magazine (this post’s graphic) has been used by Intel to promote its PCM or PRAM chips before those were spun off to Numonyx (now a part of Micron).  Intel, though, didn’t appear to have anything to share but the cover photo.

Electronics magazine went out of business in 1995, and that makes the task of finding archive copies more challenging.

It recently occurred to me that the best person to ask might be the article’s lead author, Ron Neale, who is a regular contributor to EE Times.

I was astounded to discover that Continue reading

Micron and Intel to End NAND Flash JV

Jim Handy in the IMFT fabIt came as a surprise to the Memory Guy on Monday to receive a press release from Micron indicating that Intel and Micron had decided to end their NAND flash partnership.

This agreement, which was begun in 2006, helped the two companies to aggressively ramp into the NAND flash market by combining their resources.  NAND flash makers (as well as DRAM makers) need to make very substantial capital investments to participate in the market, and that’s not easy for a new entrant.  Micron at that time was a very small NAND flash maker, and Intel wasn’t involved in the NAND flash market at all, so neither was in a position to succeed.  By combining their resources the companies were able to become important contributors to the market.

The agreement initially appeared to be modeled after the very successful joint venture that Toshiba and SanDisk enjoyed.  Each company would contribute half of the JV’s capital investment, and the same designs would be used to make both companies’ chips.

Over time Intel found itself in a familiar Continue reading

How 3D NAND Shrinks ECC Requirements

Bit Errors vs. ProcessError Correction Codes, ECC, are not only important to today’s NAND flash market, but they have been a cause of concern to NAND users for a number of years.  The Memory Guy has been intending for some time to write a low-level primer on ECC, and I am finally getting it done!

Why is ECC necessary on NAND flash, yet it’s not used for other memory technologies?  The simple answer is that NAND’s purpose is to be the absolute cheapest memory on the market, and one way to achieve the lowest-possible cost is to relax the standards for data integrity — to allow bit errors every so often.  This technique has been used for a long time in both communications channels and in hard disk drives.  Data communication systems can transfer more data using less bandwidth and a weaker signal over longer distances if they use error correction to restore distorted data.  Hard disk drives can pack more bits onto a platter if the bits don’t all have to work right.  These markets (and probably certain others) have invested a lot of money in ECC research and development, and as a result ECC today  is a very well-developed science.

Denali Software published a nice Continue reading

Micron’s Super-Fast New 32GB NVDIMM

 

Switch TrackMicron Technology has introduced a 32GB NVDIMM-N.  Perhaps the most important thing about this device is not so much its high density as the fact that it runs at higher bus speeds than competing NVDIMMs, doing 2933 megatransfers per second (MT/s), a speed that Micron representatives tell us is required to support Intel’s Skylake processor.

Up to this point NVDIMM-Ns have been limited to 2400 MT/s, which is fast enough for Broadwell, but which misses the mark for Skylake.  Design is tricky even at this slower speed, requiring a number of expensive high-speed multiplexers in the DRAM’s critical speed path.

“Multiplexers?”  Yes, NVDIMMs use them, even though no other kind of DIMM does.  The Memory Guy can explain why, having just finished a report covering the NVDIMM market and technology.

Here’s a little refresher for those who either don’t remember or never knew that NVDIMM-N requires multiplexers.  The NVDIMM-N looks to the system like a standard Continue reading

New Report Details NVDIMM Market

Objective Analysis NVDIMM Report 2017 CoverObjective Analysis has just released a new report covering the nonvolatile dual inline memory module (NVDIMM) market in detail.  This report, Profiting from the NVDIMM Market, explains the What, How, Why, & When of today’s and tomorrow’s NVDIMM products.

My readers know that I have been watching this market for some time, and that I am always perplexed as to whether to post about NVDIMMs in The Memory Guy or in The SSD Guy, since these products straddle the boundary between memory and storage.  This time my solution is to publish posts in both!

The Objective Analysis NVDIMM market model reveals that the market for NVDIMMs is poised to grow at a 105% average annual rate to nearly 12 million units by 2021.  This finding is based on a forecast methodology that has provided many of the most consistently-accurate forecasts in the semiconductor business.  This forecast, and the report itself, were compiled through exhaustive research into the technology and the events leading up to its introduction, vendor and user interviews, and briefings from standards bodies.

This 80-page in-depth analysis examines all leading NVDIMM types and forecasts their unit and revenue shipments through 2021.  Its 42 figures and 14 tables help Continue reading

Did Toshiba REALLY Lose 3-6 Weeks’ Production?

Toshiba's Fab 5 in YokkaichiYesterday The Memory Guy learned of an amazing article in DigiTimes about a 3-6 week shutdown at Toshiba’s Yokkaichi NAND flash fab line.  According to the story Toshiba’s production was shut down for 3-6 weeks accounting for a production loss of 100,000 wafers.  Another article in PC Games N converted that to lost bytes and came up with the number 400,000 terabytes.

Some quick math shows the errors in both of these articles.

First of all, the wafer stoppage.  The Toshiba/SanDisk Yokkaichi Joint Venture wafer fabrication complex processes a little over 2 million wafers per year.  Divide that by 52 weeks and you find that’s about 40,000 wafers per week, so 100,000 wafers would be 2.5 weeks’ output, not 3-6 weeks.

The number of bytes that PC Games N published takes a little more math.  According to TechInsights Toshiba’s 15nm 128Gb MLC chip has an area of 99mm².  That gets you a little over 10TB/wafer.  The company’s 48-layer TLC 256Gb part should produce about twice that.  Yet, if you divide PC Games’ Continue reading

How Samsung Will Improve 3D NAND Costs

Samsung's New Stairstep Etch iOne of the most intriguing revelations during the Flash Memory Summit two weeks ago was Samsung’s new approach to stairstep etch in 3D NAND.  This was one of numerous innovations the company’s  EVP of Flash Products & Technologies, Kye Hyun (KH) Kyung, shared during Samsung’s Tuesday Morning keynote presentation.

The Memory Guy would point readers to the pdf of Samsung’s presentation on the Flash Memory Summit website, but it isn’t there, and it’s unlikely to ever be posted there.  Samsung seems to have a policy that prohibits sharing such presentations.

Although I was unable to get a copy of the drawing that the keynoter used, I have tried to re-create it using, of all things, Excel!  The result is the graphic for this blog post.  The only thing I was unable to easily recreate was the different colors representing the layers of the 3D NAND.  You’ll need to use your imagination and envision layers of two colors, with all the surfaces exposed on the top being the same color, but at different layers of a 64-layer structure.

Today’s common approach to 3D NAND’s stairstep is to etch a simple step pattern in one dimension, which I illustrated in an early 3D NAND blog post four years ago.  This is a challenging Continue reading

3D NAND: “I Have More Layers than You Do!”

Layer CountYesterday’s news really underscored the race currently underway between 3D NAND makers to produce higher layer counts than one another.

Intel produced an announcement in which VP Rob Crooke bragged that: “Intel has delivered the world’s first commercially available 64-layer, TLC, 3D NAND solid state drive (SSD). While others have been talking about it, we have delivered.”

The announcement explained that the new Intel SSD 545s could be purchased at Newegg beginning that day.

The Memory Guy received Intel’s announcement at 10:02 AM Pacific Time.  By 3:11 PM, five hours later, there was another announcement in my “In” box, this time from Western Digital (WDC).

WDC’s e-mail announced the development of the the SanDisk/Toshiba next-generation BiCS4 3D NAND technology, with 96 layers.  The companies expect to begin to sample a 256Gb part to OEM customers in the second half of 2017 with production starting by the end of next year.

One has to wonder if WDC was Continue reading

Super-Cooled DRAM for Big Power Savings

Frozen DRAM - Hacker10Recently Rambus announced that it was using cryogenic temperatures to boost computer performance in large datacenters.  This research is being done in a joint project with Microsoft who is developing a processor based on Josephson Junctions.

This is an effort to provide a performance increases greater than can be attained through standard semiconductor scaling.  The research project aims to attain improvements in cycle time, power consumption, and compute density, leading to better energy efficiency and cost of ownership (COO).  The companies hope to gain side benefits of being able to squeeze more bits onto a DRAM chip thus reducing cost per bit, improving performance, and making DRAM chips less costly to produce.

The system these two companies are researching uses a memory system that is cooled to 77 degrees Kelvin (77°K) with a processor that operates at 4°K.  To do this the memory system is bathed in liquid nitrogen while the processor is cooled by liquid helium.  The temperatures are the boiling points of these two liquids.

Surprisingly, the fact that these two subsystems are in different Continue reading

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Jim Handy Objective Analysis Memory Market Research +1 (408) 356-2549 Jim.Handy (at) Objective-Analysis.com

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