A lone inventor has developed a data compression algorithm that defies the theoretical “Shannon Limit“. The press hasn’t covered this recent news, even though it has dramatic implications. This is probably because the technique is so very arcane. The inventor is none other than the great-great-great granddaughter of the inventor of the tabulated punch card, Herman Hollerith.
The algorithm reduces most of the data while converting the remaining information into as many ones as possible. This not only shrinks storage requirements and costs, but in the case of flash memory, it also has an important impact on total power. Flash is erased by setting all bits to ones, and bits are written by either leaving them alone (one) or by changing them (zero). The fewer zeros in the code, the less energy required to change the bits. Energy is also saved during an erase, since fewer bits need to be brought back to the erased state.
To explain the algorithm in its simplest terms, a byte of data is evaluated. If it has more zero bits than one bits the byte is inverted and an index bit is set to reflect this fact. Next, the four bits on either side of the byte are evaluated and if one has more zeros than ones it is inverted and another index bit is set. This process continues until Continue reading
The following is excerpted from an Objective Analysis Alert sent to our clients on March 26: On March 25 SanDisk and Toshiba announced sampling of their 3D NAND flash technology, a 128Gb (gigabit) 48-layer second-generation product based on the BiCS technology that the companies pioneered in 2007. Pilot production will begin in the second half of 2015 with meaningful production targeted for 2016. This release was issued at the same time that Intel and Micron were briefing the press and analysts for their March 26 announcement of their own 3D NAND offering (pictured), which is currently sampling with select customers, and is to enter full production by year-end. The Micron-Intel chip is a 32-layer 256Gb device, which the companies proudly point out is the densest flash chip in the industry.
Similarities and Differences
These two joint ventures (Intel-Micron and SanDisk-Toshiba) are taking very different Continue reading
Last week Micron and IBM announced that Micron would be IBM’s main supplier of NAND flash chips. The week before Micron announced a strategic agreement with Seagate to supply NAND flash. Why all this activity?
It comes down to today’s budding NAND flash shortage and the fact that suppliers tend to groom their customer lists when supplies get short.
Neither IBM nor Seagate represent the enormous opportunities that major consumer electronics firms like Apple do. Since many NAND suppliers are very cost-focused they look for customers that need very little support and purchase in high volumes.
IBM and Seagate look for a lot of support, and, since they both ship mostly enterprise flash systems or SSDs, they consume relatively small unit volumes of NAND flash chips.
These companies need to have an understanding of Continue reading
Last week Toshiba and SK hynix announced an agreement to jointly develop Nano Imprint Lithography (NIL), building on a memorandum of understanding (MOU) that two companies signed in December last year. Development efforts will begin this April and practical adoption is expected to start in 2017. The collaboration is expected to reduce risk and accelerate commercialization of this technology.
NIL is expected to produce next-generation lithography at high throughput rates more economically than established lithography tools. It is should compete against Extreme Ultraviolet (EUV) lithography, an alternative technology whose use has been delayed by numerous technical challenges. EUV, a euphemism for X-Rays, cannot use transmissive optics like glass lenses, so a completely new reflective imaging technology has had to be developed to support its use. The advantage of EUV is that the light wavelength is only 13nm, which is an order of magnitude smaller than the 193nm light currently used to produce leading-edge chips, allowing it to print significantly smaller features.
Unlike today’s lithography, which uses a purely photographic process, NIL mechanically stamps a pattern into the photoresist in a similar manner to the sealing wax stamp shown in the photo (courtesy of BackToZero, a wax stamp maker). The stamp is produced using Continue reading
Everspin and Northwest Logic have just announced full interoperability between Northwest Logic’s MRAM Controller Core and Everspin Technologies’ ST-MRAM (Spin-Torque Magnetic RAM) chips. This interoperability is hardware proven on a Xilinx Virtex-7 FPGA and is now available for designs needing low-latency, high memory throughput using MRAM technology.
Since The Memory Guy knew that Everspin’s EMD3D064M ST-MRAM was fully DDR3 compatible, I had to wonder why the part would require a special controller – couldn’t it simply be controlled by any DDR3 controller?
Everspin’s product marketing director, Joe O’Hare, took the time to Continue reading
The Semiconductor Industry Association this week announced the year-end World Semiconductor Trade Statistics (WSTS) revenues for 2014. Worldwide sales grew 9.9% to reach a record total of $335.8 billion, outperforming the WSTS fall forecast. Annual sales increased in all four regional markets for the first time since 2010. Memory was the fastest growing segment, increasing 18.2%, partly based on DRAM growth of 34.7%.It’s encouraging that all geographical areas experienced growth. This implies that the world economy is finally on the mend.
The industry’s 9.9% worldwide growth was a good bit lower than Objective Analysis’ December 2013 prediction of growth in excess of 20%. We admit that we overshot, expecting both higher bit growth and stronger pricing in DRAM and NAND flash than actually materialized.
The $335.8 billion number is really Continue reading
Inotera recently announced earnings and posted an impressive 55% gross margin. Inotera is a pure-play DRAM maker, so it’s not too difficult to estimate the company’s process geometries based on its financials.
The Memory Guy thought it might be interesting to determine what I could from the 55% gross margin number.
First of all we can estimate Inotera’s manufacturing cost/GB based on the gross margin and an assumption about the company’s sales price/GB. The WSTS price per gigabyte for November was $7.83. Assuming that Inotera’s ASP was equal to this number, then at a gross margin of 55% the company’s cost/GB would have been $3.52.
Inotera’s acts as a foundry for Micron Technoogy. If Inotera sold to Micron at some lower price, then Inotera’s production costs would necessarily be proportionally lower to maintain the same gross margin.
Using the WSTS price: At a processed wafer cost of $1,600 (my rule of thumb) a $3.52/GB cost would require 454 8Gb dice to be produced Continue reading
In a move touted as a merger of equals, Cypress will acquire Spansion in an all-stock transaction slated to close in the second quarter of 2015. The purchase price is estimated at $1.6 billion.
Cypress points out that it is the leading producer of SRAMs, and that Spansion is the leading NOR flash provider.
One striking feature of this transaction is the Continue reading
SanDisk co-founder Eli Harari was awarded the National Medal of Technology and Innovation on November 20 by President Obama. The medal, which was bestowed upon Dr. Harari in a White House ceremony, is the United States’ highest honor for scientific and technological achievement, and recognizes those whose lasting contributions have created a greater understanding of the world and improved the lives of many.
Harari co-founded SanDisk more that 25 years ago with the vision that flash memory would be used to store data in mobile products, a vision that initially took seed in photography in the 1990s, and has since become the fastest-growing Continue reading