Micron has announced that it is sampling a new 128Gb NAND flash chip based upon a 16nm process, with production slated for the fourth quarter. To The Memory Guy’s knowledge this is the tightest process available.
The company, with its partner Intel, gained a lead with its 20nm process generation through its use of a Hi-k tunnel dielectric, a new material that replaces more conventional silicon dioxide layer with a new material (Micron won’t say what) that yields the same capacitance with a thinner layer. This has become very important with today’s tight processes because of issues of inter-cell interference.
Other NAND makers are migrating to Continue reading
Naturally, The Memory Guy fixated on those presentations that dealt with memory. When it came to the upcoming transition to 3D NAND, AMAT had a lot to say.
A later post will explain what 3D NAND actually is. Suffice it to say that today’s approach to making NAND flash has nearly reached its limit, and the approach that manufacturers plan to use in the future involves making NAND strings that stand on their ends. This has phenomenal implications on Continue reading
SanDisk today announced that its joint venture with Toshiba would begin construction in August of its Fab 5 “phase two” shell. Completion of this Yokkaichi, Japan wafer fabrication facility is slated for mid-2014.
SanDisk expects to use this facility for technology transitions of existing Yokkaichi wafer capacity. The new clean room will provide the space for the additional equipment necessary to transition existing wafer capacity to next-generation 2D NAND technologies and to early generations of 3D NAND technology. In this way it will perform support for Fab 3, Fab 4 and phase one of Fab 5.
This is consistent with the JV’s use of Continue reading