Naturally, the first question is: “How do they do that?”
To get all the chips into the DIMM format Samsung uses TSV interconnects on the DRAMs. The module’s 36 DRAM packages each contain four 8Gb (1GB) chips, resulting in 144 DRAM chips squeezed into a standard DIMM format. Each package also includes a data buffer chip, making the stack very closely resemble either the High-Bandwidth Memory (HBM) or the Hybrid Memory Cube (HMC).
Since these 36 packages (or worse, 144 DRAM chips) would overload the processor’s address bus, the DIMM uses an RDIMM protocol – the address and control pins are buffered on the DIMM before they reach the DRAM chips, cutting the processor bus loading by an order of magnitude or more. RDIMMs are supported by certain server platforms.
At the IEEE’s IEDM conference last week Belgian research consortium imec showed an improved “gate first” 3D NAND that replaced the conventional polysilicon channel with InGaAs, Indium Gallium Arsenide, a III-V material. This new technique opens the door to higher layer counts in 3D NAND, allowing denser parts to be made in support of further cost reductions.
For those unfamiliar with the term, the “gate first” approach is the foundation of Toshiba’s BiCS NAND, and presumably Micron’s floating gate 3D NAND.
imec explains that “Replacing poly-Si as a channel material is necessary, as it is not suitable for long-term scaling.” Further they report that on-state current (ION) and transconductance (gm) of the III-V channel was better than that of polysilicon devices, without any programming, erase, or endurance degradation. The device’s characteristics are shown in this post’s graphic.
The consortium reports that the current through the Continue reading