64-Layer 3D NAND Chips Revealed at ISSCC
This week both the Toshiba-Western Digital team and Samsung disclosed details of their 64-layer 3D NAND designs at the IEEE’s International Solid-State Circuits Conference (ISSCC). The Memory Guy thought that it would be interesting to compare these two companies’ 64-layer chips against each other and against the one that Micron presented at last year’s ISSCC.
Allow me to point out that it’s no easy feat to get to 64 layers. Not only must the process build all 64 layers (or actually pairs of layers plus some additional ones for control) across the entire 300mm wafer with high uniformity and no defects, but then holes must be etched through varying materials from the top to the bottom with absolutely parallel sides at aspect ratios of about 60:1, that is, the hole is 60 times as deep as it is wide. After this the fab must deposit uniform layers of material onto the sides of these skinny holes without any variation in thickness.
None of these processes have ever been used to build any other semiconductor — it’s all brand new. This is what makes 3D NAND so challenging, and it’s why the technology is already 3 years behind its original schedule.
It’s not easy to tell from the conference papers whether or not the chips use the String Stacking approach detailed in another Memory Guy blog post. Nobody mentioned that technique. In its 2016 ISSCC paper Micron didn’t even disclose the number of layers in its chips, but the company revealed that it was a 64-layer part during a recent analyst conference and also showed a cross-section photo that revealed string stacking. My guess is that the Toshiba-WD design uses string stacking as well, but Samsung’s paper indicated that its chip did not use this approach.
Samsung instead decided to make the layers 11% thinner than those of its prior-generation products. This introduced a new set of problems: Thinning the wordline layers increased their resistance. Thinning the dielectric between them increased coupling, leading to more noise and interference while degrading retention. There were also power and loading issues that stemmed from doubling the chip’s density.
The bulk of Samsung’s paper detailed the novel techniques the researchers developed to get around these new issues. The write cache was converted to a pipelined design to accelerate write cycles. An annealing pulse is used to remove stray holes from the charge trap and improve retention. Reads are classified using a more sophisticated “Valley Tracking” scheme to accommodate drift.
Toshiba’s paper focused on reducing the die area by breaking apart the address decoders as well as improving speed and error rates by using a new shielded-bitline scheme.
How do the three products compare against each other? The table below provides a good idea of that. I used parentheses to indicate parameters that were not disclosed but that are likely:
|Cell Type||Floating Gate||Charge Trap||Charge Trap|
All three use 64 layers and 3 bits/cell effectively, yet Micron’s Gb/mm² is higher than either of the others thanks to the fact that Micron manufactures the chip’s CMOS logic circuits underneath the memory array, while its competitors put the logic alongside the array.
None of this really matters, though, until all three companies bring these products to mass production. It’s unclear at this point when that will actually occur.
Interestingly enough, all three papers started out with an explanation of why the transition to 3D NAND was necessary. Given the high technical competence of the audience, and given the fact that Toshiba introduced the 3D NAND concept over ten years ago, it is puzzling that the researchers would take the time to tell the audience something they certainly must already know.
Those who would like to gain a better understanding of 3D NAND are welcome to read the Memory Guy series: What is 3D NAND? Why do we need it? How do they make it?
Those who need a deeper understanding can contact Objective Analysis for custom consulting on this exciting technology.