Memory Manufacturers

Did Toshiba REALLY Lose 3-6 Weeks’ Production?

Toshiba's Fab 5 in YokkaichiYesterday The Memory Guy learned of an amazing article in DigiTimes about a 3-6 week shutdown at Toshiba’s Yokkaichi NAND flash fab line.  According to the story Toshiba’s production was shut down for 3-6 weeks accounting for a production loss of 100,000 wafers.  Another article in PC Games N converted that to lost bytes and came up with the number 400,000 terabytes.

Some quick math shows the errors in both of these articles.

First of all, the wafer stoppage.  The Toshiba/SanDisk Yokkaichi Joint Venture wafer fabrication complex processes a little over 2 million wafers per year.  Divide that by 52 weeks and you find that’s about 40,000 wafers per week, so 100,000 wafers would be 2.5 weeks’ output, not 3-6 weeks.

The number of bytes that PC Games N published takes a little more math.  According to TechInsights Toshiba’s 15nm 128Gb MLC chip has an area of 99mm².  That gets you a little over 10TB/wafer.  The company’s 48-layer TLC 256Gb part should produce about twice that.  Yet, if you divide PC Games’ Continue reading

64-Layer 3D NAND Chips Revealed at ISSCC

Toshiba-WD 64-Layer 3D NAND at ISSCC17This week both the Toshiba-Western Digital team and Samsung disclosed details of their 64-layer 3D NAND designs at the IEEE’s International Solid-State Circuits Conference (ISSCC)The Memory Guy thought that it would be interesting to compare these two companies’ 64-layer chips against each other and against the one that Micron presented at last year’s ISSCC.

Allow me to point out that it’s no easy feat to get to 64 layers.  Not only must the process build all 64 layers (or actually pairs of layers plus some additional ones for control) across the entire 300mm wafer with high uniformity and no defects, but then holes must be etched through varying materials from the top to the bottom with absolutely parallel sides at aspect ratios of about 60:1, that is, the hole is 60 times as deep as it is wide.  After this the fab must deposit uniform layers of material onto the sides of these skinny holes without any variation in thickness.

None of these processes have ever been used to build any other semiconductor — it’s all brand new.  This is what makes 3D NAND so challenging, and it’s why the technology is already 3 years behind its original schedule.

It’s not easy to tell from the conference papers whether or not Continue reading

Understanding Samsung’s DRAM CapEx Cut

Historical DRAM Wafer ProductionAccording to a Business Korea article Samsung announced, during a June 14 investor event, plans to reduce its DRAM capital spending and shift its focus to 3D NAND.

The Memory Guy sees this as an unsurprising move.  This post’s chart is an estimate of DRAM wafer production from 1991 through 2014.  There is a definite downtrend over the past few years.  The peak was reached in 2008 at an annual production of slightly below 15 million wafers, with a subsequent dip in 2009 thanks to the global financial collapse at the end of 2008.  After a slight recovery in 2010 the industry entered a period of steady decline.

The industry already has more than enough DRAM wafer capacity for the foreseeable future.

Why is this happening?  The answer is relatively simple: the gigabytes per wafer on a DRAM wafer are growing faster than the market’s demand for gigabytes.

Let’s dive into that in more detail.  The number of gigabytes on a DRAM wafer increases according Continue reading

Samsung Power Glitch – Is It Important?

3D NANDOn Saturday, June 18, Samsung’s Xian fab, the only facility in the world currently producing 3D NAND flash, suffered a power failure.  How much of a problem is this?

The answer really depends upon who you ask.  An article in the Financial Express quoted Samsung as saying that it would have a minimal impact, and that full-scale operations should resume in a few days.  The article also said that Samsung estimated that the wafer loss would be below 10,000 wafers.

Assuming that the entire loss consisted of Samsung’s most advanced 48-layer 256Gb 3D NAND a 10,000-wafer loss would be less than 1% of total industry gigabyte shipments.

Korea Times quoted an anonymous fund manager who said: “The one-time incident will cost Samsung up to 20 billion won, which is very minimal.  It won’t make heavy impact on Samsung’s chip business and the entire industry.”

According to Korean news source Chosenilbo the outage was caused by Continue reading

Putting DRAM Prices in Perspective

DRAM Low Spot Pricing 2011-2016For almost two years there has been a lot of worry about DRAM spot prices.  This post’s graphic plots the lowest weekly spot price per gigabyte for the cheapest DRAM, regardless of density, on a semi-logarithmic scale.  (Remember that on a semi-logarithmic scale constant growth appears as a straight line.)

The downward-sloping red line on right side of the chart shows that DRAM prices have been sliding at a 45% annual rate since October 2014.  This has a lot of people worried for the health of the industry.

What most fail to remember, though, is that DRAM spot prices hit their lowest point twice in 2011, at $2.40 in August, and then $2.20 in November.  Today’s lowest DRAM spot prices have only recently dipped below the $2.52 point hit in October of 2014.

The black dotted line in the chart is intended to focus readers’ attention on DRAM costs, which decrease at a 30% average Continue reading

Toshiba Restructuring: New 3D Fab Coming

Toshiba Yokkaichi Fab ComplexBeleaguered Toshiba finally unveiled its restructuring plan on Friday.  The plan aims to return the company to profitability and growth through management accountability.

A lot of the presentation focused on the memory business, a shining star of the Toshiba conglomerate, which has so far included appliances, nuclear power plants, and medical electronics.

Toshiba has big plans for its Semiconductor & Storage Products Company, calling it “A pillar of income with Memories as a core business”.  The company plans to enhance its NAND flash cost competitiveness by accelerating development of BiCS (Toshiba’s 3D NAND technology) and by expanding its SSD business.   There are three parts to this effort:

  1. Grow 3D NAND production capacity
  2. Speed up 3D NAND development
  3. Increase SSD development resources

This post’s graphic is an Continue reading

Goodbye, Andy Grove

Andy Grove - Only the Paranoid SurviveIt was sad to hear today of the passing of Andy Grove, Intel co-founder and former president.

Although I did not know him well, Andy was a part of my brief 1½-year stint at Intel in the early 1980s.  He played a key role in my “IOPEC” new employee training, and he and I were in cubicles on the same floor of the same Intel office building, so we would run into each other from time to time during the business day.

Plenty has been said about this man’s competence as a manager, and plenty more will be said.  He drove the creation of the world’s leading semiconductor manufacturer.

I think I was most impressed, though, when he agreed to be interviewed for a PBS television special on the history of the semiconductor industry: “Silicon Valley: American Experience” despite the fact that his battle with Parkinson’s Disease had already rendered it difficult for him to speak.

I always meant to write to him to tell him how impressed I was that he would do that.  I guess I won’t have the chance now.

Early Computer Memories

Ryszard Milewicz' photo of Core MemoryMy colleague Lane Mason found an interesting history of memories blog post that answers the question: ” What did early computers use for fast read/write storage?”

The post in the Hackaday blog, written by Al Williams, covers drum memories, the Williams Tube and its competitor the Selectron (both briefly discussed in my earlier 3D XPoint post), mercury delay lines, dekatrons, core memory (the original Storage Class Memory), plated wire memory, twistor memory, thin-film memory, and bubble memory.

It also links to interesting videos about these devices.

Think of this as a companion piece to the EE Times memory history slideshow I covered in an earlier post.  It’s a fun and educational read!

Samsung’s Colossal 128GB DIMM

Samsung_128GB TSV RDIMMIn a November 25 press release Samsung introduced a 128GB DDR4 DIMM.  This is eight times the density of the largest broadly-available DIMM and rivals the full capacity of mainstream SSDs.

Naturally, the first question is: “How do they do that?”

To get all the chips into the DIMM format Samsung uses TSV interconnects on the DRAMs.  The module’s 36 DRAM packages each contain four 8Gb (1GB) chips, resulting in 144 DRAM chips squeezed into a standard DIMM format.  Each package also includes a data buffer chip, making the stack very closely resemble either the High-Bandwidth Memory (HBM) or the Hybrid Memory Cube (HMC).

Since these 36 packages (or worse, 144 DRAM chips) would overload the processor’s address bus, the DIMM uses an RDIMM protocol – the address and control pins are buffered on the DIMM before they reach the DRAM chips, cutting the processor bus loading by an order of magnitude or more.  RDIMMs are supported by certain server platforms.

The Memory Guy asked Samsung whether Continue reading

New Report: 3D XPoint Memory

3D XPoint Report Graphic

Objective Analysis has just introduced a new report that you might want to consider: A Close Look At The Micron/Intel 3D XPoint Memory.

The report covers the Intel-Micron 3D XPoint memory and includes Intel’s new Optane support products that are based on this technology.  The report explains the technology and its special manufacturing challenges.  It includes details of how 3D XPoint memory will be used, and provides an analysis of the benefits of its persistent nature.

Forecasts project how the market will develop and include optimistic and pessimistic forecast scenarios.  Particular attention has been paid to its impact upon the DRAM, SSD, and other markets.  Finally, the report analyzes different end-market segments to predict how this technology will impact each of them.

The Memory Guy, report author Jim Handy, will present the report’s findings during the Pre-Conference Primer of the Storage Network Industry Association (SNIA) Storage Developer Conference (SDC) this Sunday, September 20, at 2:00 PM, In Santa Clara, CA.

This breakthrough report is based on Continue reading

Contact

Jim Handy Objective Analysis Memory Market Research +1 (408) 356-2549 Jim.Handy (at) Objective-Analysis.com

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