Memory Markets

Super-Cooled DRAM for Big Power Savings

Frozen DRAM - Hacker10Recently Rambus announced that it was using cryogenic temperatures to boost computer performance in large datacenters.  This research is being done in a joint project with Microsoft who is developing a processor based on Josephson Junctions.

This is an effort to provide a performance increases greater than can be attained through standard semiconductor scaling.  The research project aims to attain improvements in cycle time, power consumption, and compute density, leading to better energy efficiency and cost of ownership (COO).  The companies hope to gain side benefits of being able to squeeze more bits onto a DRAM chip thus reducing cost per bit, improving performance, and making DRAM chips less costly to produce.

The system these two companies are researching uses a memory system that is cooled to 77 degrees Kelvin (77°K) with a processor that operates at 4°K.  To do this the memory system is bathed in liquid nitrogen while the processor is cooled by liquid helium.  The temperatures are the boiling points of these two liquids.

Surprisingly, the fact that these two subsystems are in different Continue reading

US Plans Response to China’s Chip Plan

Presidential SealOn its way out the door the Obama Administration put together a proposed response to China’s plans to invest $150 billion in the semiconductor market over the next five years.  It seems that US semiconductor industry views China’s investment as a threat to its position in the market.

Last week the President’s Council of Advisors on Science and Technology (PCAST) delivered a 25-page Report to the President entitled: “Ensuring Long-Term U.S. Leadership in Semiconductors.”

You might ask: “Who is PCAST?”  The organization states its mission in this paragraph: “The President’s Council of Advisors on Science and Technology (PCAST) is an advisory group of the Nation’s leading scientists and engineers, appointed by the President to augment the science and technology advice available to him from inside the White House and from cabinet departments and other Federal agencies. PCAST is consulted about, and often makes policy recommendations concerning, the full range of issues where understandings from the domains of science, technology, and innovation bear potentially on the policy choices before the President.”

PCAST has a small Semiconductors Working Group whose elite members include Continue reading

When a Shortage Looms

DRAM Prices 1991-1997The Memory Guy has been getting calls lately asking how to tell that a shortage is developing.  My answer is always the same: It’s hard to tell.

One indicator is that spot prices which were below contract prices rise above contract prices.  This doesn’t happen for all components or densities of DRAM or NAND flash at the same time.  Some of these transitions are temporary as well.  It takes patience to see if it was a momentary change or if it was the onset of a shortage.

DRAM spot prices have generally been below contract prices since August 2014, but this month they raised above contract prices.  NAND flash spot prices also fell below contract prices in mid-2014 but today NAND’s spot price remains lower than contract prices.

Lead times represent another indicator.  If the lead time for a number of components increases then those chips are moving into a shortage.  Lead times have recently been rising for both NAND flash and DRAM.

A third indication occurs when suppliers start to Continue reading

Understanding Samsung’s DRAM CapEx Cut

Historical DRAM Wafer ProductionAccording to a Business Korea article Samsung announced, during a June 14 investor event, plans to reduce its DRAM capital spending and shift its focus to 3D NAND.

The Memory Guy sees this as an unsurprising move.  This post’s chart is an estimate of DRAM wafer production from 1991 through 2014.  There is a definite downtrend over the past few years.  The peak was reached in 2008 at an annual production of slightly below 15 million wafers, with a subsequent dip in 2009 thanks to the global financial collapse at the end of 2008.  After a slight recovery in 2010 the industry entered a period of steady decline.

The industry already has more than enough DRAM wafer capacity for the foreseeable future.

Why is this happening?  The answer is relatively simple: the gigabytes per wafer on a DRAM wafer are growing faster than the market’s demand for gigabytes.

Let’s dive into that in more detail.  The number of gigabytes on a DRAM wafer increases according Continue reading

Putting DRAM Prices in Perspective

DRAM Low Spot Pricing 2011-2016For almost two years there has been a lot of worry about DRAM spot prices.  This post’s graphic plots the lowest weekly spot price per gigabyte for the cheapest DRAM, regardless of density, on a semi-logarithmic scale.  (Remember that on a semi-logarithmic scale constant growth appears as a straight line.)

The downward-sloping red line on right side of the chart shows that DRAM prices have been sliding at a 45% annual rate since October 2014.  This has a lot of people worried for the health of the industry.

What most fail to remember, though, is that DRAM spot prices hit their lowest point twice in 2011, at $2.40 in August, and then $2.20 in November.  Today’s lowest DRAM spot prices have only recently dipped below the $2.52 point hit in October of 2014.

The black dotted line in the chart is intended to focus readers’ attention on DRAM costs, which decrease at a 30% average Continue reading

XMC Breaks Ground for 3D NAND Fab

2015 XMC campus

China foundry XMC has broken ground for its new 3D NAND flash fab, the country’s first China-owned 3D NAND flash facility.  Plans for this fab were publicly disclosed over a year ago.  Simon Yang, XMC’s CEO, gave a presentation at SEMI’s Industry Strategy Symposium (ISS) on January 11, 2015 in which he detailed the need for China to produce a larger proportion of its overall chips, explaining how his company would help make that happen.

Yang used the map in this post’s graphic to show that XMC has enough land on its campus for six 300mm wafer fabs.  Two shells (yellow), each capable of processing 30,000 wafers per month, had been constructed by that time: Fab A (left) was already fully utilized, and Fab B (right) was ready for tooling.  The gray boxes show that the site has enough space to build 2 additional 2-line megafabs, each with a capacity of up to 100k wafers per month.  Accoding to DRAMeXchange XMC currently produces 20,000 wafers of NOR flash per month.  A March 30 China Daily article reports that monthly wafer production will reach 300,000 in 2020 and 1 million in 2030.

XMC’s formal name is Wuhan Xinxin Semiconductor Manufacturing, and it is located Continue reading

Toshiba Restructuring: New 3D Fab Coming

Toshiba Yokkaichi Fab ComplexBeleaguered Toshiba finally unveiled its restructuring plan on Friday.  The plan aims to return the company to profitability and growth through management accountability.

A lot of the presentation focused on the memory business, a shining star of the Toshiba conglomerate, which has so far included appliances, nuclear power plants, and medical electronics.

Toshiba has big plans for its Semiconductor & Storage Products Company, calling it “A pillar of income with Memories as a core business”.  The company plans to enhance its NAND flash cost competitiveness by accelerating development of BiCS (Toshiba’s 3D NAND technology) and by expanding its SSD business.   There are three parts to this effort:

  1. Grow 3D NAND production capacity
  2. Speed up 3D NAND development
  3. Increase SSD development resources

This post’s graphic is an Continue reading

How NAND Flash Can Reduce DRAM Requirements

Benchmarks show NAND advantage over DRAM in PCsIn a comment to a recent Memory Guy post I stated that NAND flash can reduce DRAM requirements, even in PCs.  Some readers have told me that they wonder how this could be, so I will write this post to explain.

Some years ago Objective Analysis noticed that clever server administrators were able to use SSDs to reduce their systems’ DRAM requirements.  Not only did this save them money, but it lowered power and cooling requirements as well.

Thinking that this might work on other kinds of computers, we commissioned a number of benchmarks to be performed on a PC.

These benchmarks found that after a system already has a certain minimum amount of DRAM, users can get a bigger performance boost by adding a dollar’s worth NAND flash than they can get by adding a dollar’s worth of DRAM.

In every case the minimum amount of DRAM was very small.

This benchmark data was compiled, written up, and explained in depth in the report: How PC NAND Will Undermine DRAM, which can Continue reading

DRAM Prices Down, But Not So Bad

DRAM Spot Price per GB HistoryFor the past ten months DRAM prices have been undergoing a steady slide.  Is the market in a crisis?  Not really!

Today’s low spot price of $4.30/GB puts us on a par with February 2013, a full two years ago (see chart).  DRAM makers have done a lot to reduce their production costs since that time, so their margins this quarter will be much better than they were in the first quarter of 2013.

But we are still a very long way from the bottom of the last market downturn.  In late 2012 spot prices reached a low of $2.52/GB, a full 41% lower than today’s lowest spot prices.

The Memory Guy models the production costs of leading memory chips, and DRAM manufacturing costs have been decreasing for the past several years at an average annual rate of about 30%.  That means that costs today are about half of what they were two years ago, and one third of their level this time in 2012.

So even though today’s Continue reading

New Algorithm Dramatically Reduces Storage & Power Requirements

April Fool in BinaryA lone inventor has developed a data compression algorithm that defies the theoretical “Shannon Limit“.  The press hasn’t covered this recent news, even though it has dramatic implications.  This is probably because the technique is so very arcane.  The inventor is none other than the great-great-great granddaughter of the inventor of the tabulated punch card, Herman Hollerith.

The algorithm reduces most of the data while converting the remaining information into as many ones as possible.  This not only shrinks storage requirements and costs, but in the case of flash memory, it also has an important impact on total power.  Flash is erased by setting all bits to ones, and bits are written by either leaving them alone (one) or by changing them (zero).  The fewer zeros in the code, the less energy required to change the bits.  Energy is also saved during an erase, since fewer bits need to be brought back to the erased state.

To explain the algorithm in its simplest terms, a byte of data is evaluated.  If it has more zero bits than one bits the byte is inverted and an index bit is set to reflect this fact.  Next, the four bits on either side of the byte are evaluated and if one has more zeros than ones it is inverted and another index bit is set.  This process continues until Continue reading


Jim Handy Objective Analysis Memory Market Research +1 (408) 356-2549 Jim.Handy (at)

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