NAND Flash

Toshiba Restructuring: New 3D Fab Coming

Toshiba Yokkaichi Fab ComplexBeleaguered Toshiba finally unveiled its restructuring plan on Friday.  The plan aims to return the company to profitability and growth through management accountability.

A lot of the presentation focused on the memory business, a shining star of the Toshiba conglomerate, which has so far included appliances, nuclear power plants, and medical electronics.

Toshiba has big plans for its Semiconductor & Storage Products Company, calling it “A pillar of income with Memories as a core business”.  The company plans to enhance its NAND flash cost competitiveness by accelerating development of BiCS (Toshiba’s 3D NAND technology) and by expanding its SSD business.   There are three parts to this effort:

  1. Grow 3D NAND production capacity
  2. Speed up 3D NAND development
  3. Increase SSD development resources

This post’s graphic is an Continue reading

New Materials Solve Key 3D NAND Issue

imec III-V 3D NAND channelAt the IEEE’s IEDM conference last week Belgian research consortium imec showed an improved “gate first” 3D NAND that replaced the conventional polysilicon channel with InGaAs, Indium Gallium Arsenide, a III-V material.  This new technique opens the door to higher layer counts in 3D NAND, allowing denser parts to be made in support of further cost reductions.

For those unfamiliar with the term, the “gate first” approach is the foundation of Toshiba’s BiCS NAND, and presumably Micron’s floating gate 3D NAND.

imec explains that “Replacing poly-Si as a channel material is necessary, as it is not suitable for long-term scaling.”  Further they report that on-state current (ION) and transconductance (gm) of the III-V channel was better than that of polysilicon devices, without any programming, erase, or endurance degradation.  The device’s characteristics are shown in this post’s graphic.

The consortium reports that the current through the Continue reading

New Report: 3D XPoint Memory

3D XPoint Report Graphic

Objective Analysis has just introduced a new report that you might want to consider: A Close Look At The Micron/Intel 3D XPoint Memory.

The report covers the Intel-Micron 3D XPoint memory and includes Intel’s new Optane support products that are based on this technology.  The report explains the technology and its special manufacturing challenges.  It includes details of how 3D XPoint memory will be used, and provides an analysis of the benefits of its persistent nature.

Forecasts project how the market will develop and include optimistic and pessimistic forecast scenarios.  Particular attention has been paid to its impact upon the DRAM, SSD, and other markets.  Finally, the report analyzes different end-market segments to predict how this technology will impact each of them.

The Memory Guy, report author Jim Handy, will present the report’s findings during the Pre-Conference Primer of the Storage Network Industry Association (SNIA) Storage Developer Conference (SDC) this Sunday, September 20, at 2:00 PM, In Santa Clara, CA.

This breakthrough report is based on Continue reading

Flash Memory Summit: Limitless Layers of 3D NAND

SanDisk Technology Roadmap 2014The single most interesting thing I learned at the 2015 Flash Memory Summit was that 3D NAND doesn’t have a natural limit, after which some other memory type will need to be adopted.

For years SanDisk has been presenting a memory roadmap (this post’s graphic is one rendition) that anticipates a move to ReRAM after 3D NAND has run through its natural life, which was expected to be as little as three generations.  This has been backed by the idea that a 3D NAND stack would only be able to reach a certain number of layers before it would encounter difficulties caused by the need to etch a high aspect ratio hole through an increasing number of layers.

The aspect ratio issue is not hard to understand: Let’s assume that the hole in a 24-layer stack has an aspect ratio of 40:1, then a 32-layer hole would have an aspect ratio of about 50:1, and a 64-layer stack would be something close to 100:1.  Today’s technology starts to have trouble etching holes with an aspect ratio higher than 60:1.

These high aspect ratios were thought to be the limiting factor that would prevent 3D NAND from continuing for more than three generations.  3D NAND could only have as many layers as the aspect ratio could support.

On a panel that I moderated at this year’s Flash Memory Summit one panelist, Dr. Myoung Kwan Cho of SK hynix, explained that although there is a limit Continue reading

How Many Kinds of Memory Are There?

Micron's History of Memory TechnologiesWith Micron & Intel’s July 28 introduction of their new 3D XPoint memory both companies touted that his is the first new memory in a long time, and that the list of prior new memory types is short.

How short is that list?  Interestingly, Intel and Micron have different lists.  The Micron list, shown in this post’s graphic (click to enlarge), cites seven types: “Ram” (showing a vacuum tube), PROM, SRAM, DRAM, EPROM, NOR flash, and NAND flash.  Intel’s list adds magnetic bubble memory, making it eight.  (Definitions of these names appear in another Memory Guy blog post.)

The Memory Guy finds both lists puzzling in that they left out a number of important technologies.

For example, why did Intel neglect EEPROM, which is still in widespread use?  EEPROMs (or E²PROMs) are not only found in nearly every application that has a serial number (ranging from WiFi routers to credit cards), requires calibration (like blood glucose monitoring strips and printer ink cartridges), or provides operating parameters (i.e. the serial presence detect – SPD – in DRAM DIMMs), but they still ship in the billions of units every year.  In its time EEPROM was an important breakthrough.  Over the years EEPROM has had a much greater impact than has PROM.

And, given that both companies were willing to include tubes, a non-semiconductor technology, why did both Continue reading

Is Micron Being Acquired?

Tsinghua + Micron LogosThe following is an excerpt of an Objective Analysis Alert sent to our clients 7/13/15.

A July 13 Wall Street Journal article disclosed that China’s state-owned Tsinghua Unigroup has bid to buy Micron Technology for $21 a share or $23 billion, which would make this the largest-ever Chinese takeover of a U.S. company.

Objective Analysis has been telling our clients for the past few years that either China or India would create a new DRAM/NAND manufacturing company, especially since memory chip makers have enjoyed a long period of profits, and this usually motivates outsiders to invest in new DRAM makers.  We did not anticipate an acquisition.

Countries with heavy industry typically move into the semiconductor business during an extended upturn, and become DRAM suppliers since DRAM is an undifferentiated commodity.  Commodities sell almost solely on price and success is based on little more than manufacturing strength.  This is a business model that industrial economies understand.

In addition to Micron’s tangible assets, including Continue reading

How NAND Flash Can Reduce DRAM Requirements

Benchmarks show NAND advantage over DRAM in PCsIn a comment to a recent Memory Guy post I stated that NAND flash can reduce DRAM requirements, even in PCs.  Some readers have told me that they wonder how this could be, so I will write this post to explain.

Some years ago Objective Analysis noticed that clever server administrators were able to use SSDs to reduce their systems’ DRAM requirements.  Not only did this save them money, but it lowered power and cooling requirements as well.

Thinking that this might work on other kinds of computers, we commissioned a number of benchmarks to be performed on a PC.

These benchmarks found that after a system already has a certain minimum amount of DRAM, users can get a bigger performance boost by adding a dollar’s worth NAND flash than they can get by adding a dollar’s worth of DRAM.

In every case the minimum amount of DRAM was very small.

This benchmark data was compiled, written up, and explained in depth in the report: How PC NAND Will Undermine DRAM, which can Continue reading

What Memory Will Intel’s Purley Platform Use?

Part of Intel Purley SlideThere has been quite a lot of interest over the past few days about the apparently-inadvertent disclosure by Intel of its server platform roadmap.  Detailed coverage in The Platform showed a couple of slides with key memory information for the upcoming Purley server platform which will support the Xeon “Skylake” processor family.  (A review of this post on 7/13/17 revealed that The Platform’s website has disappeared.  The above link and the next one no longer work.)

One slide, titled: “Purley: Biggest Platform Advancement Since Nehalem” includes this post’s graphic, which tells of a memory with: “Up to 4x the capacity & lower cost than DRAM, and 500x faster than NAND.”

The Memory Guy puzzled a bit about what this might be.  The only memory chip technology today with a cost structure lower than that of DRAM is NAND flash, and there is unlikely to be any technology within the leaked roadmap’s 2015-2017 time span that will change that.  MRAM, ReRAM, PCM, FRAM, and other technologies can’t beat DRAM’s cost, and will probably take close to a decade to get to that point.

Since that’s the case, then what is this mystery memory?  If we think of Continue reading

New Algorithm Dramatically Reduces Storage & Power Requirements

April Fool in BinaryA lone inventor has developed a data compression algorithm that defies the theoretical “Shannon Limit“.  The press hasn’t covered this recent news, even though it has dramatic implications.  This is probably because the technique is so very arcane.  The inventor is none other than the great-great-great granddaughter of the inventor of the tabulated punch card, Herman Hollerith.

The algorithm reduces most of the data while converting the remaining information into as many ones as possible.  This not only shrinks storage requirements and costs, but in the case of flash memory, it also has an important impact on total power.  Flash is erased by setting all bits to ones, and bits are written by either leaving them alone (one) or by changing them (zero).  The fewer zeros in the code, the less energy required to change the bits.  Energy is also saved during an erase, since fewer bits need to be brought back to the erased state.

To explain the algorithm in its simplest terms, a byte of data is evaluated.  If it has more zero bits than one bits the byte is inverted and an index bit is set to reflect this fact.  Next, the four bits on either side of the byte are evaluated and if one has more zeros than ones it is inverted and another index bit is set.  This process continues until Continue reading

Four New Players Join 3D NAND Market

Micron & Intel's 3D NAND Die PhotoThe following is excerpted from an Objective Analysis Alert sent to our clients on March 26: On March 25 SanDisk and Toshiba announced sampling of their 3D NAND flash technology, a 128Gb (gigabit) 48-layer second-generation product based on the BiCS technology that the companies pioneered in 2007.  Pilot production will begin in the second half of 2015 with meaningful production targeted for 2016. This release was issued at the same time that Intel and Micron were briefing the press and analysts for their March 26 announcement of their own 3D NAND offering (pictured), which is currently sampling with select customers, and is to enter full production by year-end.  The Micron-Intel chip is a 32-layer 256Gb device, which the companies proudly point out is the densest flash chip in the industry.

Similarities and Differences

These two joint ventures (Intel-Micron and SanDisk-Toshiba) are taking very different Continue reading

Contact

Jim Handy Objective Analysis Memory Market Research +1 (408) 356-2549 Jim.Handy (at) Objective-Analysis.com

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