Technical Trends

Memsys: A New Memory Conference

1999 White HouseSince I am the Memory Guy I hate learning that I missed something new and cool in the world of memories, but somehow I was unaware of last week’s Memsys conference in Washington DC until a participant notified me on Saturday that his paper: “Reverse Engineering of DRAMs: Row Hammer with Crosshair,” had been given the the best paper award.

Upon looking at the Memsys website it looks like a very intriguing academic conference.  about sixty papers were presented in eight interesting sessions:

  • Issues in High Performance Computing
  • Nonvolatile Main Memories and DRAM Caches, Parts I & II
  • Hybrid Memory Cube and Alternative DRAM Channels
  • Thinking Outside the Box
  • Improving the DRAM Device Architecture
  • Issues and Interconnects for 2.5D and 3D Packaging
  • Some Amazingly Cool Physical Experiments

in addition to a few apparently-fascinating keynotes.

Fortunately, all of the papers are Continue reading

Samsung Power Glitch – Is It Important?

3D NANDOn Saturday, June 18, Samsung’s Xian fab, the only facility in the world currently producing 3D NAND flash, suffered a power failure.  How much of a problem is this?

The answer really depends upon who you ask.  An article in the Financial Express quoted Samsung as saying that it would have a minimal impact, and that full-scale operations should resume in a few days.  The article also said that Samsung estimated that the wafer loss would be below 10,000 wafers.

Assuming that the entire loss consisted of Samsung’s most advanced 48-layer 256Gb 3D NAND a 10,000-wafer loss would be less than 1% of total industry gigabyte shipments.

Korea Times quoted an anonymous fund manager who said: “The one-time incident will cost Samsung up to 20 billion won, which is very minimal.  It won’t make heavy impact on Samsung’s chip business and the entire industry.”

According to Korean news source Chosenilbo the outage was caused by Continue reading

Toshiba Restructuring: New 3D Fab Coming

Toshiba Yokkaichi Fab ComplexBeleaguered Toshiba finally unveiled its restructuring plan on Friday.  The plan aims to return the company to profitability and growth through management accountability.

A lot of the presentation focused on the memory business, a shining star of the Toshiba conglomerate, which has so far included appliances, nuclear power plants, and medical electronics.

Toshiba has big plans for its Semiconductor & Storage Products Company, calling it “A pillar of income with Memories as a core business”.  The company plans to enhance its NAND flash cost competitiveness by accelerating development of BiCS (Toshiba’s 3D NAND technology) and by expanding its SSD business.   There are three parts to this effort:

  1. Grow 3D NAND production capacity
  2. Speed up 3D NAND development
  3. Increase SSD development resources

This post’s graphic is an Continue reading

A 1T SRAM? Sounds Too Good to be True!

Zeno 1T SRAMAt the IEEE’s International Electron Device Meeting (IEDM) in December a start-up named Zeno Semiconductors introduced a 1-transistor (1T) SRAM.  Given that today’s SRAMs generally use between six and eight transistors per bit, this alternative promises to squeeze the same amount of SRAM into a space 1/6th to 1/8th the size of current SRAM designs, leading to significant cost savings.

The device is really a single standard NMOS transistor that behaves as if it were two bipolar transistors connected into something like a flip-flop, although the transistors’ bases are open, rather than cross-coupled to the opposite transistors’ collector, as is done in a standard flip-flop.

The cell is selected by activating the gate, and the bit is set or sensed via the source and drain to provide a differential signal.

This is a decidedly clever departure from standard SRAM configurations, and it reflects a careful observation of the actual Continue reading

Samsung’s Colossal 128GB DIMM

Samsung_128GB TSV RDIMMIn a November 25 press release Samsung introduced a 128GB DDR4 DIMM.  This is eight times the density of the largest broadly-available DIMM and rivals the full capacity of mainstream SSDs.

Naturally, the first question is: “How do they do that?”

To get all the chips into the DIMM format Samsung uses TSV interconnects on the DRAMs.  The module’s 36 DRAM packages each contain four 8Gb (1GB) chips, resulting in 144 DRAM chips squeezed into a standard DIMM format.  Each package also includes a data buffer chip, making the stack very closely resemble either the High-Bandwidth Memory (HBM) or the Hybrid Memory Cube (HMC).

Since these 36 packages (or worse, 144 DRAM chips) would overload the processor’s address bus, the DIMM uses an RDIMM protocol – the address and control pins are buffered on the DIMM before they reach the DRAM chips, cutting the processor bus loading by an order of magnitude or more.  RDIMMs are supported by certain server platforms.

The Memory Guy asked Samsung whether Continue reading

New Materials Solve Key 3D NAND Issue

imec III-V 3D NAND channelAt the IEEE’s IEDM conference last week Belgian research consortium imec showed an improved “gate first” 3D NAND that replaced the conventional polysilicon channel with InGaAs, Indium Gallium Arsenide, a III-V material.  This new technique opens the door to higher layer counts in 3D NAND, allowing denser parts to be made in support of further cost reductions.

For those unfamiliar with the term, the “gate first” approach is the foundation of Toshiba’s BiCS NAND, and presumably Micron’s floating gate 3D NAND.

imec explains that “Replacing poly-Si as a channel material is necessary, as it is not suitable for long-term scaling.”  Further they report that on-state current (ION) and transconductance (gm) of the III-V channel was better than that of polysilicon devices, without any programming, erase, or endurance degradation.  The device’s characteristics are shown in this post’s graphic.

The consortium reports that the current through the Continue reading

Flash Memory Summit: Limitless Layers of 3D NAND

SanDisk Technology Roadmap 2014The single most interesting thing I learned at the 2015 Flash Memory Summit was that 3D NAND doesn’t have a natural limit, after which some other memory type will need to be adopted.

For years SanDisk has been presenting a memory roadmap (this post’s graphic is one rendition) that anticipates a move to ReRAM after 3D NAND has run through its natural life, which was expected to be as little as three generations.  This has been backed by the idea that a 3D NAND stack would only be able to reach a certain number of layers before it would encounter difficulties caused by the need to etch a high aspect ratio hole through an increasing number of layers.

The aspect ratio issue is not hard to understand: Let’s assume that the hole in a 24-layer stack has an aspect ratio of 40:1, then a 32-layer hole would have an aspect ratio of about 50:1, and a 64-layer stack would be something close to 100:1.  Today’s technology starts to have trouble etching holes with an aspect ratio higher than 60:1.

These high aspect ratios were thought to be the limiting factor that would prevent 3D NAND from continuing for more than three generations.  3D NAND could only have as many layers as the aspect ratio could support.

On a panel that I moderated at this year’s Flash Memory Summit one panelist, Dr. Myoung Kwan Cho of SK hynix, explained that although there is a limit Continue reading

Micron/Intel 3D XPoint Raises More Questions than Answers

Micron-Intel 3D XPoint Memory InternalsMicron and Intel hosted an event in San Francisco Tuesday, July 28, to introduce a new memory technology that they have named “3D XPoint”.  This technology was explained to be “up to 1,000 times faster, with 1,000 times the endurance of NAND flash” while being significantly cheaper than DRAM.

Some technical details:

  • 3D XPoint is a “Fundamentally Different Technology” than current memory types.  It’s an ReRAM that uses material property changes for bit storage where both DRAM and NAND use charge to store a bit
  • The chip currently stores 128Gb in two stacked planes of 64Gb each, storing a single bit per cell
    • Today’s densest production NAND flash chips store 128GB by using MLC, so this chip actually has twice as many bit cells as any production NAND flash
    • The companies do not see a clear limit to the number of planes they can stack, but are optimistic about this
  • The bulk mechanism can be used to store multiple bits on a single cell (MLC)
  • Today’s chip is made using a 20nm process, but can scale well past that
    • There is no clear limit of how far the technology can be scaled
  • It’s 1,000 times faster than NAND flash and offers 1,000 times NAND’s endurance
  • It’s 10 times as dense as today’s “Conventional Memory” (which I suppose to be DRAM)
  • This is not intended to replace either NAND or DRAM, but to coexist as a new memory layer between NAND and DRAM

The companies claim that other Continue reading

Four New Players Join 3D NAND Market

Micron & Intel's 3D NAND Die PhotoThe following is excerpted from an Objective Analysis Alert sent to our clients on March 26: On March 25 SanDisk and Toshiba announced sampling of their 3D NAND flash technology, a 128Gb (gigabit) 48-layer second-generation product based on the BiCS technology that the companies pioneered in 2007.  Pilot production will begin in the second half of 2015 with meaningful production targeted for 2016. This release was issued at the same time that Intel and Micron were briefing the press and analysts for their March 26 announcement of their own 3D NAND offering (pictured), which is currently sampling with select customers, and is to enter full production by year-end.  The Micron-Intel chip is a 32-layer 256Gb device, which the companies proudly point out is the densest flash chip in the industry.

Similarities and Differences

These two joint ventures (Intel-Micron and SanDisk-Toshiba) are taking very different Continue reading

What’s This Nano-Imprint Litho that Toshiba and SK hynix are Co-Developing?

BackToZero Sealing WaxLast week Toshiba and SK hynix announced an agreement to jointly develop Nano Imprint Lithography (NIL), building on a memorandum of understanding (MOU) that two companies signed in December last year.  Development efforts will begin this April and practical adoption is expected to start in 2017.  The collaboration is expected to reduce risk and accelerate commercialization of this technology.

NIL is expected to produce next-generation lithography at high throughput rates more economically than established lithography tools.  It is should compete against Extreme Ultraviolet (EUV) lithography, an alternative technology whose use has been delayed by numerous technical challenges.  EUV, a euphemism for X-Rays, cannot use transmissive optics like glass lenses, so a completely new reflective imaging technology has had to be developed to support its use.  The advantage of EUV is that the light wavelength is only 13nm, which is an order of magnitude smaller than the 193nm light currently used to produce leading-edge chips, allowing it to print significantly smaller features.

Unlike today’s lithography, which uses a purely photographic process, NIL mechanically stamps a pattern into the photoresist in a similar manner to the sealing wax stamp shown in the photo (courtesy of BackToZero, a wax stamp maker).  The stamp is produced using Continue reading


Jim Handy Objective Analysis Memory Market Research +1 (408) 356-2549 Jim.Handy (at)

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