Tomorrow’s Memory Technologies

Memsys: A New Memory Conference

1999 White HouseSince I am the Memory Guy I hate learning that I missed something new and cool in the world of memories, but somehow I was unaware of last week’s Memsys conference in Washington DC until a participant notified me on Saturday that his paper: “Reverse Engineering of DRAMs: Row Hammer with Crosshair,” had been given the the best paper award.

Upon looking at the Memsys website it looks like a very intriguing academic conference.  about sixty papers were presented in eight interesting sessions:

  • Issues in High Performance Computing
  • Nonvolatile Main Memories and DRAM Caches, Parts I & II
  • Hybrid Memory Cube and Alternative DRAM Channels
  • Thinking Outside the Box
  • Improving the DRAM Device Architecture
  • Issues and Interconnects for 2.5D and 3D Packaging
  • Some Amazingly Cool Physical Experiments

in addition to a few apparently-fascinating keynotes.

Fortunately, all of the papers are Continue reading

Intel Developer Forum – Not Much 3D XPoint Progress

IDF16 FaceAfter a big 3D XPoint launch one year ago almost anyone would expect for Intel to have had a lot of exciting new news to share about the technology at last week’s Intel Developer Forum (IDF).  Those who were watching for that, though, were in for a disappointment.

For readers who don’t remember, Intel and its partner, chipmaker Micron Technology, announced a new memory layer in July 2015 that would enable in-memory databases to expand well beyond the constraints posed by standard DRAM memory. The pair also boasted the additional benefit of being nonvolatile or persistent – data would not be lost if the power failed.  This technology promised to open new horizons in the world of computing.

Intel devoted a lot of effort to promotion and education during the following month’s IDF, and even demonstrated a prototype 3D XPoint SSD that performed seven to eight times as fast as Intel’s highest-performance existing NAND flash SSD – the DC S3700.  Although a DIMM form factor was disclosed, no prototypes were on hand.  Both were given the brand name “Optane”.

Moving forward one year to the 2016 IDF (the source of this post’s odd graphic), The Memory Guy was shown Continue reading

IBM Jumps on the “New Memory” Bandwagon

IBM's 3-Bit PCM Read AlgorithmAt a technical conference hosted by the IEEE this week IBM announced the results of nearly a decade of research in which its scientists have been investigating the emerging technology known as “Phase Change Memory” (PCM).  The scientists presented a means of successfully storing three bits per cell for the first time, while also addressing all of PCM’s challenging idiosyncrasies, including resistance drift and temperature drift.

Commonly referred to by the erroneous nickname “TLC” for Triple Level Cell, this technology squeezes three bits of data into the space of a single bit, essentially cutting the cost per gigabyte to about one third of that of a standard memory chip making it closer in cost to flash.

With this step IBM expects to help drive a new memory layer into existence, one that will fit between the cheap and slow NAND flash used in SSDs and the fast but expensive DRAM used for main memory.  Such a layer would improve the cost/performance of all types of Continue reading

Toshiba Restructuring: New 3D Fab Coming

Toshiba Yokkaichi Fab ComplexBeleaguered Toshiba finally unveiled its restructuring plan on Friday.  The plan aims to return the company to profitability and growth through management accountability.

A lot of the presentation focused on the memory business, a shining star of the Toshiba conglomerate, which has so far included appliances, nuclear power plants, and medical electronics.

Toshiba has big plans for its Semiconductor & Storage Products Company, calling it “A pillar of income with Memories as a core business”.  The company plans to enhance its NAND flash cost competitiveness by accelerating development of BiCS (Toshiba’s 3D NAND technology) and by expanding its SSD business.   There are three parts to this effort:

  1. Grow 3D NAND production capacity
  2. Speed up 3D NAND development
  3. Increase SSD development resources

This post’s graphic is an Continue reading

A 1T SRAM? Sounds Too Good to be True!

Zeno 1T SRAMAt the IEEE’s International Electron Device Meeting (IEDM) in December a start-up named Zeno Semiconductors introduced a 1-transistor (1T) SRAM.  Given that today’s SRAMs generally use between six and eight transistors per bit, this alternative promises to squeeze the same amount of SRAM into a space 1/6th to 1/8th the size of current SRAM designs, leading to significant cost savings.

The device is really a single standard NMOS transistor that behaves as if it were two bipolar transistors connected into something like a flip-flop, although the transistors’ bases are open, rather than cross-coupled to the opposite transistors’ collector, as is done in a standard flip-flop.

The cell is selected by activating the gate, and the bit is set or sensed via the source and drain to provide a differential signal.

This is a decidedly clever departure from standard SRAM configurations, and it reflects a careful observation of the actual Continue reading

Crossbar or Crosspoint?

Computing Crossbar SwitchThe Memory Guy has recently run across a point of confusion between two very similar terms: Crossbar and Crosspoint.

A crosspoint memory is a memory where a bit cell resides at every intersection of a wordline and a bitline.  It’s the smallest way you can make a memory cell.  Think of the wordlines and bitlines as the wires in a window screen.  If there’s a bit everywhere they cross, then it’s a crosspoint memory.

In most cases a crossbar is a communication path in a computing system.  (Of course, there are exceptions, the main one being a company, Crossbar Inc., that is developing a crosspoint memory technology!) A crossbar communication path is topographically similar to a crosspoint, but its function is to connect a number of memory arrays to a number of processors.  Visualize a vertical column of memory arrays named A, B, C… and a horizontal row of processors named 1, 2, 3… as is illustrated in this post’s graphic.  The crossbar can connect Processor 1 to Memory A, or to any other memory that is not already connected to another processor.  These connections are represented by the circles in the diagram.  You can see that this is an efficient way to allow processors to share a memory space to achieve very high speed inter-processor communications.

Crossbars are quite likely to Continue reading

New Report: 3D XPoint Memory

3D XPoint Report Graphic

Objective Analysis has just introduced a new report that you might want to consider: A Close Look At The Micron/Intel 3D XPoint Memory.

The report covers the Intel-Micron 3D XPoint memory and includes Intel’s new Optane support products that are based on this technology.  The report explains the technology and its special manufacturing challenges.  It includes details of how 3D XPoint memory will be used, and provides an analysis of the benefits of its persistent nature.

Forecasts project how the market will develop and include optimistic and pessimistic forecast scenarios.  Particular attention has been paid to its impact upon the DRAM, SSD, and other markets.  Finally, the report analyzes different end-market segments to predict how this technology will impact each of them.

The Memory Guy, report author Jim Handy, will present the report’s findings during the Pre-Conference Primer of the Storage Network Industry Association (SNIA) Storage Developer Conference (SDC) this Sunday, September 20, at 2:00 PM, In Santa Clara, CA.

This breakthrough report is based on Continue reading

How Many Kinds of Memory Are There?

Micron's History of Memory TechnologiesWith Micron & Intel’s July 28 introduction of their new 3D XPoint memory both companies touted that his is the first new memory in a long time, and that the list of prior new memory types is short.

How short is that list?  Interestingly, Intel and Micron have different lists.  The Micron list, shown in this post’s graphic (click to enlarge), cites seven types: “Ram” (showing a vacuum tube), PROM, SRAM, DRAM, EPROM, NOR flash, and NAND flash.  Intel’s list adds magnetic bubble memory, making it eight.  (Definitions of these names appear in another Memory Guy blog post.)

The Memory Guy finds both lists puzzling in that they left out a number of important technologies.

For example, why did Intel neglect EEPROM, which is still in widespread use?  EEPROMs (or E²PROMs) are not only found in nearly every application that has a serial number (ranging from WiFi routers to credit cards), requires calibration (like blood glucose monitoring strips and printer ink cartridges), or provides operating parameters (i.e. the serial presence detect – SPD – in DRAM DIMMs), but they still ship in the billions of units every year.  In its time EEPROM was an important breakthrough.  Over the years EEPROM has had a much greater impact than has PROM.

And, given that both companies were willing to include tubes, a non-semiconductor technology, why did both Continue reading

Micron/Intel 3D XPoint Raises More Questions than Answers

Micron-Intel 3D XPoint Memory InternalsMicron and Intel hosted an event in San Francisco Tuesday, July 28, to introduce a new memory technology that they have named “3D XPoint”.  This technology was explained to be “up to 1,000 times faster, with 1,000 times the endurance of NAND flash” while being significantly cheaper than DRAM.

Some technical details:

  • 3D XPoint is a “Fundamentally Different Technology” than current memory types.  It’s an ReRAM that uses material property changes for bit storage where both DRAM and NAND use charge to store a bit
  • The chip currently stores 128Gb in two stacked planes of 64Gb each, storing a single bit per cell
    • Today’s densest production NAND flash chips store 128GB by using MLC, so this chip actually has twice as many bit cells as any production NAND flash
    • The companies do not see a clear limit to the number of planes they can stack, but are optimistic about this
  • The bulk mechanism can be used to store multiple bits on a single cell (MLC)
  • Today’s chip is made using a 20nm process, but can scale well past that
    • There is no clear limit of how far the technology can be scaled
  • It’s 1,000 times faster than NAND flash and offers 1,000 times NAND’s endurance
  • It’s 10 times as dense as today’s “Conventional Memory” (which I suppose to be DRAM)
  • This is not intended to replace either NAND or DRAM, but to coexist as a new memory layer between NAND and DRAM

The companies claim that other Continue reading

Avalanche Samples MRAM

AVALANCHE TECHNOLOGY, INC. LOGO

Today Avalanche Technology announced that it is sampling MRAM, making it the world’s second company to actually produce this much-researched technology.

For those unfamiliar with MRAM, it is one of a number of technologies being positioned to replace currently-entrenched memory technologies once they reach their scaling limits.  Regular Memory Guy readers know that this juncture has been anticipated for a few decades, but always seems to get postponed.

MRAM, like many other alternative technologies, offers the promise of scaling beyond the limits of DRAM and NAND to become cheaper than ether of these technologies.  Add to this its fast write speed, low power, lack of refresh, nearly unlimited endurance, and nonvolatility, and it becomes a very compelling alternative over the long term.

As opposed to the other MRAM-maker Everspin, Avalanche’s MRAM uses Continue reading

Contact

Jim Handy Objective Analysis Memory Market Research +1 (408) 356-2549 Jim.Handy (at) Objective-Analysis.com

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