Tomorrow’s Memory Technologies

Latest White Paper: New Memories for Efficient Computing

A Potpourri of Emerging MemoriesThere has been a lot of discussion in the trade press lately about new memory technologies.  This is with good reason: Existing memory technologies are approaching a limit after which bits can’t be shrunk any smaller, and that limit would put an end to Moore’s Law.

But there are even more compelling reasons for certain applications to convert from today’s leading technologies (like NAND flash, DRAM, NOR flash, SRAM, and EEPROM) to one of these new technologies, and that is the fact that the newer technologies all provide considerable energy savings in computing environments.

Objective Analysis has just published a white paper that can be downloaded for free which addresses a number of these technologies.  The white paper explains why energy is wasted with today’s technologies and how these new memory types can dramatically reduce energy consumption.

It also provides a Continue reading

Storage/Memory Hierarchy 40 Years Ago

1978 Memory/Storage HierarchyLast year I stumbled upon something on the Internet that I thought would be fun to share.  It’s the picture on the left from a 1978 book by Laurence Allman: Memory Design Microcomputers to Mainframes.  The picture’s not too clear, but it is a predecessor to a graphic of the memory/storage hierarchy that The Memory Guy often uses to explain how various elements (HDD, SSD, DRAM) fit together.

On the horizontal axis is Access Time, which the storage community calls latency.  The vertical axis shows cost per bit.  The chart uses a log-log format: both the X and Y axes are in orders of magnitude.  This allows a straight line to be drawn through the points that represent the various technologies, and prevent most of the technologies from being squeezed into the bottom left corner of the chart.

What I find fascinating about this graphic is not only the technologies that it includes but also the way that it’s presented.  First, let’s talk about the technologies.

At the very top we have RAM: “TTL, ECL, and fast MOS static types.”  TTL and ECL, technologies that are seldom Continue reading

Wafer Shortages and DRAM/NAND

Mark Thirsk, Linx ConsultingRecently I have been hearing concerns that an impending wafer shortage might drive today’s DRAM and NAND flash shortages to epic proportions.

The Memory Guy doesn’t pretend to have any understanding of the raw wafer business, so I decided to consult Mark Thirsk, managing partner of Linx Consulting.  Mark has been in this industry for quite a while and has a very good understanding of the ongoing status of the semiconductor materials supply chain.

Mark and I were on a panel together at SEMICON Korea in February, and he presented an interesting chart to compare the costs of different technologies.  I asked him about this chart as well.

Here’s what Mark had to say:

“Our information is that major Continue reading

Original PCM Article from 1970

For a number of years The Memory Guy has wanted to find a copy of the 1970 article, published in Electronics magazine, in which Intel’s Gordon Moore and two authors from Energy Conversion Devices, Ron Neale and D.L. Nelson, showed that PCM could be used as a memory device.  After all, this is the technology behind Micron & Intel’s 3D XPoint Memory.

The cover of the magazine (this post’s graphic) has been used by Intel to promote its PCM or PRAM chips before those were spun off to Numonyx (now a part of Micron).  Intel, though, didn’t appear to have anything to share but the cover photo.

Electronics magazine went out of business in 1995, and that makes the task of finding archive copies more challenging.

It recently occurred to me that the best person to ask might be the article’s lead author, Ron Neale, who is a regular contributor to EE Times.

I was astounded to discover that Continue reading

New Report Details NVDIMM Market

Objective Analysis NVDIMM Report 2017 CoverObjective Analysis has just released a new report covering the nonvolatile dual inline memory module (NVDIMM) market in detail.  This report, Profiting from the NVDIMM Market, explains the What, How, Why, & When of today’s and tomorrow’s NVDIMM products.

My readers know that I have been watching this market for some time, and that I am always perplexed as to whether to post about NVDIMMs in The Memory Guy or in The SSD Guy, since these products straddle the boundary between memory and storage.  This time my solution is to publish posts in both!

The Objective Analysis NVDIMM market model reveals that the market for NVDIMMs is poised to grow at a 105% average annual rate to nearly 12 million units by 2021.  This finding is based on a forecast methodology that has provided many of the most consistently-accurate forecasts in the semiconductor business.  This forecast, and the report itself, were compiled through exhaustive research into the technology and the events leading up to its introduction, vendor and user interviews, and briefings from standards bodies.

This 80-page in-depth analysis examines all leading NVDIMM types and forecasts their unit and revenue shipments through 2021.  Its 42 figures and 14 tables help Continue reading

Examining 3D XPoint’s 1,000 Times Endurance Benefit

3D XPoint Endurance GraphicThe Memory Guy, as a regular reader of The SSD Guy’s posts, found an interesting one that compares the endurance of Optane SSDs against that of NAND flash SSDs.  Perhaps this could provide some insight into the Intel & Micron claim that 3D XPoint Memory’s endurance is 1,000 times that of standard NAND flash, shown in the graphic to the left.

The SSD Guy post converts several different measures of SSD endurance against each other: TBW, DWPD, and GB/Day.  Definitions of these terms can be found in that post.

It occurred to me that any of these can be used to roughly gauge the relative endurance of 3D XPoint Memory against that of NAND flash.

Take DWPD for example: Drive Writes per Day.  Not only is this a measure of how many times that an SSD can be over-written every day, but it’s also an indication of the number of times that each memory cell can be overwritten.  If you know this, and if you know how long Continue reading

Memsys: A New Memory Conference

1999 White HouseSince I am the Memory Guy I hate learning that I missed something new and cool in the world of memories, but somehow I was unaware of last week’s Memsys conference in Washington DC until a participant notified me on Saturday that his paper: “Reverse Engineering of DRAMs: Row Hammer with Crosshair,” had been given the the best paper award.

Upon looking at the Memsys website it looks like a very intriguing academic conference.  about sixty papers were presented in eight interesting sessions:

  • Issues in High Performance Computing
  • Nonvolatile Main Memories and DRAM Caches, Parts I & II
  • Hybrid Memory Cube and Alternative DRAM Channels
  • Thinking Outside the Box
  • Improving the DRAM Device Architecture
  • Issues and Interconnects for 2.5D and 3D Packaging
  • Some Amazingly Cool Physical Experiments

in addition to a few apparently-fascinating keynotes.

Fortunately, all of the papers are Continue reading

Intel Developer Forum – Not Much 3D XPoint Progress

IDF16 FaceAfter a big 3D XPoint launch one year ago almost anyone would expect for Intel to have had a lot of exciting new news to share about the technology at last week’s Intel Developer Forum (IDF).  Those who were watching for that, though, were in for a disappointment.

For readers who don’t remember, Intel and its partner, chipmaker Micron Technology, announced a new memory layer in July 2015 that would enable in-memory databases to expand well beyond the constraints posed by standard DRAM memory. The pair also boasted the additional benefit of being nonvolatile or persistent – data would not be lost if the power failed.  This technology promised to open new horizons in the world of computing.

Intel devoted a lot of effort to promotion and education during the following month’s IDF, and even demonstrated a prototype 3D XPoint SSD that performed seven to eight times as fast as Intel’s highest-performance existing NAND flash SSD – the DC S3700.  Although a DIMM form factor was disclosed, no prototypes were on hand.  Both were given the brand name “Optane”.

Moving forward one year to the 2016 IDF (the source of this post’s odd graphic), The Memory Guy was shown Continue reading

IBM Jumps on the “New Memory” Bandwagon

IBM's 3-Bit PCM Read AlgorithmAt a technical conference hosted by the IEEE this week IBM announced the results of nearly a decade of research in which its scientists have been investigating the emerging technology known as “Phase Change Memory” (PCM).  The scientists presented a means of successfully storing three bits per cell for the first time, while also addressing all of PCM’s challenging idiosyncrasies, including resistance drift and temperature drift.

Commonly referred to by the erroneous nickname “TLC” for Triple Level Cell, this technology squeezes three bits of data into the space of a single bit, essentially cutting the cost per gigabyte to about one third of that of a standard memory chip making it closer in cost to flash.

With this step IBM expects to help drive a new memory layer into existence, one that will fit between the cheap and slow NAND flash used in SSDs and the fast but expensive DRAM used for main memory.  Such a layer would improve the cost/performance of all types of Continue reading

Toshiba Restructuring: New 3D Fab Coming

Toshiba Yokkaichi Fab ComplexBeleaguered Toshiba finally unveiled its restructuring plan on Friday.  The plan aims to return the company to profitability and growth through management accountability.

A lot of the presentation focused on the memory business, a shining star of the Toshiba conglomerate, which has so far included appliances, nuclear power plants, and medical electronics.

Toshiba has big plans for its Semiconductor & Storage Products Company, calling it “A pillar of income with Memories as a core business”.  The company plans to enhance its NAND flash cost competitiveness by accelerating development of BiCS (Toshiba’s 3D NAND technology) and by expanding its SSD business.   There are three parts to this effort:

  1. Grow 3D NAND production capacity
  2. Speed up 3D NAND development
  3. Increase SSD development resources

This post’s graphic is an Continue reading


Jim Handy Objective Analysis Memory Market Research +1 (408) 356-2549 Jim.Handy (at)

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