Everspin and Northwest Logic have just announced full interoperability between Northwest Logic’s MRAM Controller Core and Everspin Technologies’ ST-MRAM (Spin-Torque Magnetic RAM) chips. This interoperability is hardware proven on a Xilinx Virtex-7 FPGA and is now available for designs needing low-latency, high memory throughput using MRAM technology.
Since The Memory Guy knew that Everspin’s EMD3D064M ST-MRAM was fully DDR3 compatible, I had to wonder why the part would require a special controller – couldn’t it simply be controlled by any DDR3 controller?
Everspin’s product marketing director, Joe O’Hare, took the time to Continue reading
In a move touted as a merger of equals, Cypress will acquire Spansion in an all-stock transaction slated to close in the second quarter of 2015. The purchase price is estimated at $1.6 billion.
Cypress points out that it is the leading producer of SRAMs, and that Spansion is the leading NOR flash provider.
One striking feature of this transaction is the Continue reading
Wiley has recently published a new book by Betty Prince titled Vertical 3D NAND Technologies that is one to consider if you want to bring yourself up to speed on recent research behind today’s and tomorrow’s 3D memory technologies.
For those who haven’t previously encountered Dr. Prince, she is the author of a number of key books covering memory design and holds memory patents written over her 30-year career in the field.
The book provides capsule summaries of over 360 papers and articles from scholarly journals on the subject of 3D memories, including DRAM, NAND flash, and stacked chips.
These papers are organized into Continue reading
Although the course was very well received, I never posted a link to it on The Memory Guy blog. This post is intended to correct that error.
The course runs 75 minutes and covers the basics of DRAM, non-volatile RAM, SRAM, NAND flash, NOR flash, mask ROM, and EEPROM. It explains each technology’s advances in size, cost and performance, leading up to the development of Continue reading
Only months after Samsung’s announcement of 3D memory production a new 4-dimensional memory has been prototyped by university researchers. This memory not only has bits in the X and Y dimensions, like planar NAND, and the Z dimension, like 3D NAND, but it also grows in capacity over time, spanning the fourth dimension: time.
This research has been spearheaded by George P. Burdell, Assistant Associate Professor pro tem at Death Valley University. The work is the culmination of a decades-long effort to find a way to increase memory sizes in systems without the need to replace chips or modules.
The team has created the name “Growing RAM” or “GRAM” for the technology. Current prototypes exhibit very favorable Continue reading
Crossbar says that the technology can put a terabyte onto a single chip. The company has already measured filaments as thin as 6nm, and is confident that it can be shrunk further and that it will support multilevel cells.
Crossbar’s device is a silver filament ReRAM with a difference. For one, the silver filaments are in standard silicon dioxide, probably the most Continue reading
In a new cross-disciplinary effort, researchers have developed a novel approach to attach bonding wires to stacks of memory chips. The new technique, being called a “breakthrough” by its developers, promises to allow chips to be stacked to several times their current 8-chip and 16-chip heights.
At issue is the challenge of precisely bonding wires a fraction of the diameter of a human hair over great distances without their inadvertently coming into contact with their neighbors to create a short circuit. Such a short could destroy one or more of the chips in the stack, rendering the entire stack useless. The mechanical means of attaching these wires, although highly sophisticated, still has significant issues, that limit the economics of higher stacks.
Researchers at the Berea University of Geology (BUG) in Berea, Kentucky, noticed that certain Continue reading
In brief: Macronix’ researchers buried a heater in the array to heat the tunnel dielectric, annealing out the disruptions & traps that might cause a bit to fail.
A prototype has so far been tested more than 100 million cycles and it shows no sign of impending failure. Researchers believe that it is likely to reach one billion or more cycles, but such testing will take several months. This just may be able to Continue reading
EE Times has published a very interesting slideshow called: A Brief History of Memory by Kristin Lewotsky. This is recommended reading for all who peruse of The Memory Guy blog. Even the comments are good reading, with one commenter sharing a history of ferroelectrics that dates back to the 1950s.
It’s interesting to see the Continue reading