Crossbar says that the technology can put a terabyte onto a single chip. The company has already measured filaments as thin as 6nm, and is confident that it can be shrunk further and that it will support multilevel cells.
Crossbar’s device is a silver filament ReRAM with a difference. For one, the silver filaments are in standard silicon dioxide, probably the most Continue reading
In a new cross-disciplinary effort, researchers have developed a novel approach to attach bonding wires to stacks of memory chips. The new technique, being called a “breakthrough” by its developers, promises to allow chips to be stacked to several times their current 8-chip and 16-chip heights.
At issue is the challenge of precisely bonding wires a fraction of the diameter of a human hair over great distances without their inadvertently coming into contact with their neighbors to create a short circuit. Such a short could destroy one or more of the chips in the stack, rendering the entire stack useless. The mechanical means of attaching these wires, although highly sophisticated, still has significant issues, that limit the economics of higher stacks.
Researchers at the Berea University of Geology (BUG) in Berea, Kentucky, noticed that certain Continue reading
In brief: Macronix’ researchers buried a heater in the array to heat the tunnel dielectric, annealing out the disruptions & traps that might cause a bit to fail.
A prototype has so far been tested more than 100 million cycles and it shows no sign of impending failure. Researchers believe that it is likely to reach one billion or more cycles, but such testing will take several months. This just may be able to Continue reading
EE Times has published a very interesting slideshow called: A Brief History of Memory by Kristin Lewotsky. This is recommended reading for all who peruse of The Memory Guy blog. Even the comments are good reading, with one commenter sharing a history of ferroelectrics that dates back to the 1950s.
It’s interesting to see the Continue reading
For the past decade or so memory researchers have been looking to Spin Transfer Torque (sometimes called “Spin Torque Transfer”) MRAMs as a way of getting to tighter processes than conventional toggle MRAM. It seems that current densities in toggle MRAM rise too high as the process shrinks – at some point the process could no longer scale since chips would burn themselves out during programming. The ST-RAM paves Everspin’s path toward Continue reading
Lane Mason of Objective Analysis recently shared with The Memory Guy an article he wrote for the 4 April 2007 Denali Memory Report covering Phase Change Memory (PCM or PRAM.) It looked like something big was about to happen with the technology: PCM looked nearly ready to enter production.
Here it is 2012, and PCM represents little more than a drop in the bucket when it comes to memory sales, although Continue reading
After years of prototyping Micron Technology claims to be the first to introduce production volumes of Phase-Change Memory, or PCM. This memory, also known as PRAM, has long been positioned as a contender to replace flash once flash reaches its scaling limit. Rather than use electrons to store a bit, PCM uses a type of glass that is conductive when in a crystalline state and resistive when amorphous, two states that are relatively easy to control. The size of the bits can shrink to a very small dimensions, allowing PCM to scale into the single-digit number of nanometers, which most folks today believe to be beyond the realm of flash.
This product began its life at Intel, then followed the Numonyx spin-off, and was taken over by Micron when it acquired Numonyx. In fact, Intel got into PCM very early on – this post’s graphic is the cover of an Electronics Magazine from September 1970 with an Intel story, written by Gordon Moore, telling about a 128-bit PCM research chip.
So far only three companies have produced samples Continue reading
An acquaintance recently brought to my attention an article in R&D Magazine about some pioneering research on phase-change memories or PCM. The researchers’ findings hold a lot of promise. (R&D Magazine’s article is based upon an original paper in the journal Science.)
A team led by Ritesh Agarwal, associate professor at the University of Pennsylvania, was trying to develop a better understanding of the mechanism behind the phase changes in PCM. The team found that existing programming algorithms that involve melting the material could be replaced with pulses of electrical current that not only would program the cell without heat, but provided an “On” to “Off” resistance ratio of 2-3 orders of magnitude, which renders the cell significantly easier to read, especially in the presence of noise. This effectively makes memory chip design Continue reading
Everyone knows that flash memory is about to hit its scaling limit – it’s right around the corner. We’re ready for it because it’s been right around the corner for more than a decade now. It’s so close we can taste it.
When will it happen?
One thing that is quite clear is that nobody knows when NAND flash will stop scaling. Everyone knows that it’s soon, but researchers continue to find ways to push the technology another couple of process nodes past where anyone thought it could possibly go, and they have been doing this since Continue reading