Since I am the Memory Guy I hate learning that I missed something new and cool in the world of memories, but somehow I was unaware of last week’s Memsys conference in Washington DC until a participant notified me on Saturday that his paper: “Reverse Engineering of DRAMs: Row Hammer with Crosshair,” had been given the the best paper award.
Upon looking at the Memsys website it looks like a very intriguing academic conference. about sixty papers were presented in eight interesting sessions:
- Issues in High Performance Computing
- Nonvolatile Main Memories and DRAM Caches, Parts I & II
- Hybrid Memory Cube and Alternative DRAM Channels
- Thinking Outside the Box
- Improving the DRAM Device Architecture
- Issues and Interconnects for 2.5D and 3D Packaging
- Some Amazingly Cool Physical Experiments
in addition to a few apparently-fascinating keynotes.
Fortunately, all of the papers are Continue reading
After a big 3D XPoint launch one year ago almost anyone would expect for Intel to have had a lot of exciting new news to share about the technology at last week’s Intel Developer Forum (IDF). Those who were watching for that, though, were in for a disappointment.
For readers who don’t remember, Intel and its partner, chipmaker Micron Technology, announced a new memory layer in July 2015 that would enable in-memory databases to expand well beyond the constraints posed by standard DRAM memory. The pair also boasted the additional benefit of being nonvolatile or persistent – data would not be lost if the power failed. This technology promised to open new horizons in the world of computing.
Intel devoted a lot of effort to promotion and education during the following month’s IDF, and even demonstrated a prototype 3D XPoint SSD that performed seven to eight times as fast as Intel’s highest-performance existing NAND flash SSD – the DC S3700. Although a DIMM form factor was disclosed, no prototypes were on hand. Both were given the brand name “Optane”.
At a technical conference hosted by the IEEE this week IBM announced the results of nearly a decade of research in which its scientists have been investigating the emerging technology known as “Phase Change Memory” (PCM). The scientists presented a means of successfully storing three bits per cell for the first time, while also addressing all of PCM’s challenging idiosyncrasies, including resistance drift and temperature drift.
Commonly referred to by the erroneous nickname “TLC” for Triple Level Cell, this technology squeezes three bits of data into the space of a single bit, essentially cutting the cost per gigabyte to about one third of that of a standard memory chip making it closer in cost to flash.
With this step IBM expects to help drive a new memory layer into existence, one that will fit between the cheap and slow NAND flash used in SSDs and the fast but expensive DRAM used for main memory. Such a layer would improve the cost/performance of all types of Continue reading
The Memory Guy has recently run across a point of confusion between two very similar terms: Crossbar and Crosspoint.
A crosspoint memory is a memory where a bit cell resides at every intersection of a wordline and a bitline. It’s the smallest way you can make a memory cell. Think of the wordlines and bitlines as the wires in a window screen. If there’s a bit everywhere they cross, then it’s a crosspoint memory.
In most cases a crossbar is a communication path in a computing system. (Of course, there are exceptions, the main one being a company, Crossbar Inc., that is developing a crosspoint memory technology!) A crossbar communication path is topographically similar to a crosspoint, but its function is to connect a number of memory arrays to a number of processors. Visualize a vertical column of memory arrays named A, B, C… and a horizontal row of processors named 1, 2, 3… as is illustrated in this post’s graphic. The crossbar can connect Processor 1 to Memory A, or to any other memory that is not already connected to another processor. These connections are represented by the circles in the diagram. You can see that this is an efficient way to allow processors to share a memory space to achieve very high speed inter-processor communications.
Crossbars are quite likely to Continue reading
Objective Analysis has just introduced a new report that you might want to consider: A Close Look At The Micron/Intel 3D XPoint Memory.
The report covers the Intel-Micron 3D XPoint memory and includes Intel’s new Optane support products that are based on this technology. The report explains the technology and its special manufacturing challenges. It includes details of how 3D XPoint memory will be used, and provides an analysis of the benefits of its persistent nature.
Forecasts project how the market will develop and include optimistic and pessimistic forecast scenarios. Particular attention has been paid to its impact upon the DRAM, SSD, and other markets. Finally, the report analyzes different end-market segments to predict how this technology will impact each of them.
The Memory Guy, report author Jim Handy, will present the report’s findings during the Pre-Conference Primer of the Storage Network Industry Association (SNIA) Storage Developer Conference (SDC) this Sunday, September 20, at 2:00 PM, In Santa Clara, CA.
This breakthrough report is based on Continue reading
How short is that list? Interestingly, Intel and Micron have different lists. The Micron list, shown in this post’s graphic (click to enlarge), cites seven types: “Ram” (showing a vacuum tube), PROM, SRAM, DRAM, EPROM, NOR flash, and NAND flash. Intel’s list adds magnetic bubble memory, making it eight. (Definitions of these names appear in another Memory Guy blog post.)
The Memory Guy finds both lists puzzling in that they left out a number of important technologies.
For example, why did Intel neglect EEPROM, which is still in widespread use? EEPROMs (or E²PROMs) are not only found in nearly every application that has a serial number (ranging from WiFi routers to credit cards), requires calibration (like blood glucose monitoring strips and printer ink cartridges), or provides operating parameters (i.e. the serial presence detect – SPD – in DRAM DIMMs), but they still ship in the billions of units every year. In its time EEPROM was an important breakthrough. Over the years EEPROM has had a much greater impact than has PROM.
And, given that both companies were willing to include tubes, a non-semiconductor technology, why did both Continue reading
There has been quite a lot of interest over the past few days about the apparently-inadvertent disclosure by Intel of its server platform roadmap. Detailed coverage in The Platform showed a couple of slides with key memory information for the upcoming Purley server platform which will support the Xeon “Skylake” processor family.
One slide, titled: “Purley: Biggest Platform Advancement Since Nehalem” includes this post’s graphic, which tells of a memory with: “Up to 4x the capacity & lower cost than DRAM, and 500x faster than NAND.”
The Memory Guy puzzled a bit about what this might be. The only memory chip technology today with a cost structure lower than that of DRAM is NAND flash, and there is unlikely to be any technology within the leaked roadmap’s 2015-2017 time span that will change that. MRAM, ReRAM, PCM, FRAM, and other technologies can’t beat DRAM’s cost, and will probably take close to a decade to get to that point.
Since that’s the case, then what is this mystery memory? If we think of memory systems, rather than memory chips we can come up with one very plausible answer. Intel may be very Continue reading
Wiley has recently published a new book by Betty Prince titled Vertical 3D NAND Technologies that is one to consider if you want to bring yourself up to speed on recent research behind today’s and tomorrow’s 3D memory technologies.
For those who haven’t previously encountered Dr. Prince, she is the author of a number of key books covering memory design and holds memory patents written over her 30-year career in the field.
The book provides capsule summaries of over 360 papers and articles from scholarly journals on the subject of 3D memories, including DRAM, NAND flash, and stacked chips.
These papers are organized into Continue reading
Although the course was very well received, I never posted a link to it on The Memory Guy blog. This post is intended to correct that error.
The course runs 75 minutes and covers the basics of DRAM, non-volatile RAM, SRAM, NAND flash, NOR flash, mask ROM, and EEPROM. It explains each technology’s advances in size, cost and performance, leading up to the development of Continue reading