Comparing Samsung V-NAND to Micron 16nm Planar NAND

Andrew Walker, SchiltronI was recently directed to a very interesting blog post written by 3D technologist Andrew Walker of Schiltron in which he compares two NAND flash chips that were presented at the IEEE International Solid State Circuits Conference (ISSCC) on February 12.

The post, titled Samsung’s V-NAND Flash at the 2014 ISSCC: Ye Distant Spires… is on the 3D InCites website.

Dr. Walker puts a lot more time and effort into his graphic representations of 3D NAND chips than do others (The Memory Guy included) and this makes it much easier to understand the issues he points out.  He shows us that Samsung’s 3D NAND cell is about 5 times the size of a 40nm planar NAND cell and about 30 times that of Micron’s 16nm planar cell, and that the 3D NAND’s physical area is unlikely to change with any future 3D technology generations.

For this and other reasons (given in the article) he states that the Samsung V-NAND is “an impressive achievement but not a realistic foundation for the future.”

After having compiled my series on 3D NAND I can appreciate Dr. Walker’s opinion.  This is certainly going to be a difficult technology to master, and it could be quite some time before the cost structure for 3D NAND can compete against that of today’s planar technologies.

Give the Walker post a quick read and judge for yourself whether we are at the brink of a 3D conversion or if this technology can be expected to slip out a few years.

5 Responses to Comparing Samsung V-NAND to Micron 16nm Planar NAND

  • dr.no says:

    How is his logic even considered if 20 nm had degradation in MTBF? So he is saying 16 nm is better than 40 nm in size, but does that even matter if pricing is stuck and can’t go down even if they could get 10 nm and 1 million MTBF? Nothing is free.

    Whole point of 3d was to not reduce process size but stack vertically.

    If 2d could do the job no one would be even spending one red cent on 3d stacking.

    • JimHandy says:

      Dr.No, Thanks for the comment.

      You are right – nobody would develop 3D if 2D could scale and continue to reduce production costs.

      NAND makers believe that 2D can no longer reduce costs, so they are looking for help from 3D. That is why Toshiba named this approach “Bit Cost Scaling” (BiCS) when they invented it in 2006. Even though the process will stop scaling, the cost of a bit will continue to decrease.

      Jim

  • Andy Walker says:

    Thank you Dr. No for your comment.

    Of course 3D is the answer to the halt in 3D NAND scaling. The question is, which 3D?

    V-NAND (and Toshiba’s BiCS/p-BiCS) are being touted as the lowest cost approaches in 3D. The whole point of my IEEE paper and subsequent analyses is to show that this assumption rests on shaky grounds at best.

    Regards – Andy

  • Abhijit says:

    Hi Andy:

    So in your view, looks like VNAND is not the only immediate rescue and has its own limitation to scale, so what do you feel the next 3D will be?

    • Andy Walker says:

      Thanks for your excellent question Abhijit. I think what is dawning on people (some earlier than others) is that these “litho-light” approaches to 3D Flash have their own specific issues in cost and performance such that a more litho-intensive approach becomes attractive in comparison. Anything in this regard that uses industry standard materials, tools, programming and erase mechanisms and design techniques that can lead to laterally scalable solutions in 3D is then probably the path. Let me leave it at that since otherwise it may smack of a simple plug for my company :)

      Best regards – Andy

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