Finally! Samsung’s 3-Bit V-NAND Arrives

3-bit V-NANDSamsung has finally introduced the 3-bit 3D NAND chip it revealed at last August’s Flash Memory Summit.  This announcement was made in the form of an SSD announcement.

For those who were unable to attend the Flash Memory Summit, Samsung’s Senior VP of Memory R&D, Bob Brennan, announced in his keynote speech that a 3D 32-layer V-NAND, a chip that would achieve twice the chip density of planar NAND, was entering production and that SSDs would follow in a month.  Now, two months later, Samsung has announced those SSDs.

This week’s release reiterates Mr. Brennan’s statement about the chip’s greater density, saying: “Compared to Samsung’s 10 nanometer-class* 3-bit planar NAND flash, the new 3-bit V-NAND has more than doubled wafer productivity.”  (That little asterisk by the words: “10 nanometer-class*” is Samsung’s way of telling you that it’s not really 10nm.  This approach doesn’t work – the press usually gives the company credit for shipping more advanced technologies than Samsung actually produces.)

The new V-NAND chip appears to be the 3-bit rendition of the 86Gb density MLC chip that the Samsung used to roll out its first V-NAND SSD, the 850, in early July.  At the time some reviewers wondered about the odd non-binary density of the chips, but some in the industry understood that since 86Gb is two times 43Gb, and since 128Gb is roughly three times 43Gb, then the chip must have been designed to be a 128Gb device, but that Samsung decided to start shipments with a more conservative 2-bit MLC version.

ChipWorks dissected one of these 86Gb V-NAND chips and tells us that the die size is about 85mm².   Samsung’s 128Gb 19nm TLC K9ADGD8U0M NAND chip has a die area of 144mm², which is close to double the V-NAND chip’s 85mm², so Mr. Brennan’s statement is about right.

Brennan, in his keynote, explained that V-NAND had low cell-to-cell interference, and that this would support the use of 3-bit MLC.  He told of a 10X reduction in errors due to threshold overlap, which is the problem that has prevented the use of 3-bit and 4-bit MLC in most applications.

In all it’s a laudable accomplishment to produce SSDs with any 3D NAND, particularly 3-bit V-NAND.  It will be some fun to follow Samsung’s progress in this area, since the whole point of 3D NAND is to reduce costs below the level that can be reached with standard planar NAND.  Samsung’s financials will show whether the company’s progress in this area has been a success.

Leave a Reply

Your email address will not be published. Required fields are marked *

Contact

Jim Handy Objective Analysis Memory Market Research +1 (408) 356-2549 Jim.Handy (at) Objective-Analysis.com

Translate to:

Website Translation GTS Translation