Four New Players Join 3D NAND Market

Micron & Intel's 3D NAND Die PhotoThe following is excerpted from an Objective Analysis Alert sent to our clients on March 26: On March 25 SanDisk and Toshiba announced sampling of their 3D NAND flash technology, a 128Gb (gigabit) 48-layer second-generation product based on the BiCS technology that the companies pioneered in 2007.  Pilot production will begin in the second half of 2015 with meaningful production targeted for 2016. This release was issued at the same time that Intel and Micron were briefing the press and analysts for their March 26 announcement of their own 3D NAND offering (pictured), which is currently sampling with select customers, and is to enter full production by year-end.  The Micron-Intel chip is a 32-layer 256Gb device, which the companies proudly point out is the densest flash chip in the industry.

Similarities and Differences

These two joint ventures (Intel-Micron and SanDisk-Toshiba) are taking very different approaches to 3D, both of which also differ from Samsung’s currently-shipping V-NAND.  Toshiba and SanDisk are staying very true to the BiCS (“Bit Cost Scaling”) charge trap architecture that Toshiba first announced in 2007, while Micron and Intel are using a floating gate design whose details have not yet been revealed. Both Samsung’s V-NAND and Toshiba’s BiCS use a charge trap, which is a convneient way of circumventing any need to pattern a floating gate.  Since it is difficult to pattern any vertical structure, most NAND makers see a charge trap as the simplest way to produce a 3D NAND string. Micron and Intel argue that their floating gate alternative takes advantage of years of floating gate experience, a 44-year-old technology. Both the Toshiba 128Gb and the Micron 256Gb 3D NAND chips are 2-bit MLC, while Samsung’s 128Gb part stores three bits per cell.

Coincidental Timing

The Memory Guy feels compelled to make some mention of the timing of these two announcements.  Like the Samsung and SK hynix DRAM 8Gb LPDDR4 announcements in December 2013, which were released only an hour apart, the timing of these announcements leads to questions about whether there was a leak from one camp that drove a response from the other.  There is no indication of any other triggering event that would have caused these announcements to be synchronized.

Why 3D?  Why Now?

Conventional planar NAND flash is approaching its “scaling limit”, a point beyond which it can no longer be cost-reduced by shrinking the production process.  3D NAND is the industry’s approach to continue to cost-reduce NAND flash along its current trajectory for another few generations.  For an in-depth explanation of this technology is available on The Memory Guy blog.   Objective Analysis publishes reports detailing NAND flash and SSD markets.  These reports can be purchased for immediate download from our website.

3 Responses to Four New Players Join 3D NAND Market

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  • Tom Lee says:

    Dose 3D NAND have source/drain junction for memory cells? Or it uses junction-less structure? I do not see any source/drain doping to make the source/drain junction in any of your 3D NAND process. Thanks.

    • Jim Handy says:

      Tom Lee,

      You’re correct: There’s no source and drain for the channel transistors. This is one of the 12+ issues that make 3D NAND so difficult to manufacture efficiently.

      I am not deep enough to be able to explain how this works, so I asked Betty Prince, PhD, the author of “Vertical 3D Memory Technology” ISBN 978-1-118-76045-1 http://www.wiley.com/WileyCDA/WileyTitle/productCd-1118760514.html

      Dr. Prince knows EVERYTHING about memory!

      She reminded me that the explanation was in the book on page 88-94 which covers Junctionless Gate-All-Around Nanowire SONOS memories.

      Dr. Prince explains that there is no room for a source or drain implant between gates on a vertical nanowire and the field inversion effect, which simulates the drain and source implants, is produced by the transistor gate. Figure 3.26 on page 91 shows the virtual source/drain caused by the gate field effect. Figure 3.30 on page 93 shows the electron concentration along the string between gates.

      I read this book and posted a brief review here: http://TheMemoryGuy.com/new-book-vertical-3d-memory-technologies/

      I should probably go back and review it. It’s a great source of all kinds of information!

      Thanks for reading the Memory Guy blog.

      Jim

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