Samsung’s View on Charge Trap Flash
At the Flash Memory Summit yesterday ES Jung, PhD, EVP & GM for the Samsung R&D Center, explained the inner workings of Samsung’s new V-NAND vertical NAND flash technology. I will shortly be writing a series to explain what a 3D NAND is since there is little on the web that gives clear details about the technology.
One key attribute of most 3D NAND approaches is the use of a charge trapping layer. This has to do with the difficulty of manufacturing sideways floating gates.
Dr Jung delighted the show’s audience by explaining that a standard floating gate is like water, where electrons can freely move, and may leak out, while a charge trap is like cheese in which the electrons are barely able to move. His diagram is the graphic for this post.
I have known about charge trapping since 2002 when AMD and Fujitsu introdced their MirrorBit NOR flash, but this is the first time I have seen any analogy made between a charge trap and cheese!
It’s a good explanation, and one that I will have to remember in the future.