Naturally, the first question is: “How do they do that?”
To get all the chips into the DIMM format Samsung uses TSV interconnects on the DRAMs. The module’s 36 DRAM packages each contain four 8Gb (1GB) chips, resulting in 144 DRAM chips squeezed into a standard DIMM format. Each package also includes a data buffer chip, making the stack very closely resemble either the High-Bandwidth Memory (HBM) or the Hybrid Memory Cube (HMC).
Since these 36 packages (or worse, 144 DRAM chips) would overload the processor’s address bus, the DIMM uses an RDIMM protocol – the address and control pins are buffered on the DIMM before they reach the DRAM chips, cutting the processor bus loading by an order of magnitude or more. RDIMMs are supported by certain server platforms.
The graphic for this post (click to enlarge), supplied by ASML, the semiconductor industry’s leading lithography tool supplier, illustrates the challenge of migrating from one process node to the next. Across the bottom, on the X-axis, are representative process nodes ranging from “2D-45”, or two-dimensional (planar) 45nm NAND, to “3D-5x”, or three-dimensional 5xnm NAND. Below these numbers are the year of volume production.
The vertical axis, labeled “Tolerance” represents the minimum Continue reading
Every so often something very strange happens that puzzles The Memory Guy. On December 29 (or Dec. 30 in Seoul) something odd occurred.
I received two e-mails, one from SK hynix at 3:55 PM Pacific Time, and one from Samsung exactly one hour later. Both were press releases.
The SK hynix release was titled: “SK Hynix Developed the World’s First Next Generation Mobile Memory LPDDR4”. It announced that the company is sampling its 20nm-class 8Gb LPDDR4 DRAM to customers.
The Samsung release was Continue reading
Micron has announced that it is sampling a new 128Gb NAND flash chip based upon a 16nm process, with production slated for the fourth quarter. To The Memory Guy’s knowledge this is the tightest process available.
The company, with its partner Intel, gained a lead with its 20nm process generation through its use of a Hi-k tunnel dielectric, a new material that replaces more conventional silicon dioxide layer with a new material (Micron won’t say what) that yields the same capacitance with a thinner layer. This has become very important with today’s tight processes because of issues of inter-cell interference.
Other NAND makers are migrating to Continue reading
The companies introduced their new “1y” processing node that, according to SanDisk, produces 19nm x 19.5nm cell, versus the earlier “19nm” process (or “1x”) that used a 19nm x 26nm cell.
The graphic for this post (click to enlarge) was presented during SanDisk’s May 5th Analyst Day and compares the 24nm process to the 19 x 26nm process, moving to the 19 x 19nm process, and eventually to “1z” which neither company is yet revealing. After the 1z process SanDisk believes Continue reading
Micron Technology and Intel announced today (6 December, 2011) that the two companies are sampling a 128 gigabit (that’s 16 gigabytes) NAND flash chip manufactured by the company’s IMFT joint venture.
This is a doubling of the capacity of the 64Gb chip the companies announced in April, but they assure us that the size of the die hasn’t doubled, and the accompanying photo supports this. Intel tells us that the die will fit into standard BGA and TSOP packages. Continue reading