35nm

Why NAND is So Difficult to Scale

ASML chart chowing the lithography used for 4X, 3X, 2X, and 1Xnm planar NAND and 3D NANDNAND flash is the process leader in memory technology, and this puts it in a very challenging position: It must ramp to high volume production using techniques that have never been tried before.

The graphic for this post (click to enlarge), supplied by ASML, the semiconductor industry’s leading lithography tool supplier, illustrates the challenge of migrating from one process node to the next.  Across the bottom, on the X-axis, are representative process nodes ranging from “2D-45”, or two-dimensional (planar) 45nm NAND, to “3D-5x”, or three-dimensional 5xnm NAND.  Below these numbers are the year of volume production.

The vertical axis, labeled “Tolerance” represents the minimum Continue reading

Samsung DRAMs in Massive Leibniz SuperMUC

The Leibniz Supercomputing Centre's SuperMUC supercomputerToday Samsung announced that its chips are used exclusively to make up the 324-terabytes of DRAM in Germany’s new Leibniz Supercomputing Centre SuperMUC supercomputer.

Samsung’s release tells us that the SuperMUC, the most powerful supercomputer system in Europe, is an IBM System x iDataPlex dx360 M4 server built using over 18,000 Intel Xeon CPUs and over 80,000 4GB DRAM modules from Samsung.  (Simple math makes this out to be 82,944 modules.)

That looks like a lot of silicon!  Let’s see how much that might be.

A 4GB parity DRAM module would use nine 4Gb DRAM chips, which Samsung appears to Continue reading

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Jim Handy Objective Analysis Memory Market Research +1 (408) 356-2549 Jim.Handy (at) Objective-Analysis.com

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