Bit Cost Scaling

New Materials Solve Key 3D NAND Issue

imec III-V 3D NAND channelAt the IEEE’s IEDM conference last week Belgian research consortium imec showed an improved “gate first” 3D NAND that replaced the conventional polysilicon channel with InGaAs, Indium Gallium Arsenide, a III-V material.  This new technique opens the door to higher layer counts in 3D NAND, allowing denser parts to be made in support of further cost reductions.

For those unfamiliar with the term, the “gate first” approach is the foundation of Toshiba’s BiCS NAND, and presumably Micron’s floating gate 3D NAND.

imec explains that “Replacing poly-Si as a channel material is necessary, as it is not suitable for long-term scaling.”  Further they report that on-state current (ION) and transconductance (gm) of the III-V channel was better than that of polysilicon devices, without any programming, erase, or endurance degradation.  The device’s characteristics are shown in this post’s graphic.

The consortium reports that the current through the Continue reading

Why NAND is So Difficult to Scale

ASML chart chowing the lithography used for 4X, 3X, 2X, and 1Xnm planar NAND and 3D NANDNAND flash is the process leader in memory technology, and this puts it in a very challenging position: It must ramp to high volume production using techniques that have never been tried before.

The graphic for this post (click to enlarge), supplied by ASML, the semiconductor industry’s leading lithography tool supplier, illustrates the challenge of migrating from one process node to the next.  Across the bottom, on the X-axis, are representative process nodes ranging from “2D-45”, or two-dimensional (planar) 45nm NAND, to “3D-5x”, or three-dimensional 5xnm NAND.  Below these numbers are the year of volume production.

The vertical axis, labeled “Tolerance” represents the minimum Continue reading

How Do You Erase and Program 3D NAND?

How FN Tunneling WorksSome of my readers have asked: “How is 3D NAND programmed and erased?  Is it any different from planar NAND?”

In a word: No.

(Before I get too far into this allow me to admit that The Memory Guy doesn’t understand quantum physics, so I will be presenting this only to the depth that I understand it.  There will be no band-gap diagrams or equations to wrestle with.)

Both 3D NAND and planar NAND use Fowler Nordheim Tunneling (FN) to both program and erase.  This differs from NOR flash which programs bits using Continue reading

3D NAND: How do You Access the Control Gates?

Samsung's TCAT NAND Flash Wordline COnnectionsOne of the thornier problems in making 3D NAND is the job of connecting the peripheral logic (the row decoders) to all of those control gates that are on layers buried somewhere within the bit array.  Remember that the control gates are the conductive sheets of polysilicon or tantalum nitride at various depths in the chip.

The problem boils down to this: You can’t run connections from each layer up or down the side of the chip to get to the CMOS circuits below.  Instead you have to create a terrace structure to expose and connect to each layer.

These connections are made by etching a stair-step pattern into the layers and sinking Continue reading

An Alternative Kind of Vertical 3D NAND String

Samsung's TCAT 3D NAND flashMy prior 3D NAND post explained how Toshiba’s BiCS cell works, using a silicon nitride charge trap to substitute for a floating gate.  This post will look at an alternative technology used by Samsung and Hynix which is illustrated in the first graphic, a diagram Samsung presented at a technical conference. This cell also uses a charge trap.

Let The Memory Guy warn you, if the process in my prior post seemed tricky, this one promises to put that one to shame!

Part of this stems from the use of a different kind of NAND bit cell.  You can shrink flash cells smaller if you use a high-k gate dielectric (one with a high dielectric constant “k”) since it Continue reading

3D NAND: Making a Vertical String

Toshiba's Original BiCS Diagram - IEDM 2007Let’s look at how one form of 3D NAND is manufactured.  For this post we will explore the original design suggested by Toshiba at the IEEE’s International Electron Device Meeting (IEDM) in 2007.  It’s shown in the first graphic of this post.  (Click on any of the graphics for a better view.)

Toshiba calls this technology “BiCS” for “Bit Cost Scaling.”  The technique doesn’t scale the process the way the world of semiconductors has always done to date – it scales the cost without shrinking the length and width of the memory cell.  It accomplishes this by going vertically, as is shown in this post’s first graphic.

This takes a special effort. This is where the real Continue reading

What is 3D NAND? Why do we need it? How do they make it?

3D NANDIn August 2013 Samsung announced its V-NAND, the first production 3D NAND, kicking off a big change in the way that NAND flash will be manufactured.  This new technology raises a number of important questions:

  • What exactly is a 3D NAND?
  • Why does the industry need to go to a 3D topology?
  • How the heck do they make such a product?

To answer these questions I assembled a series of articles posted as weekly segments on The Memory Guy blog during the fourth quarter of 2013.  The different sections are listed below, with hot links to each section.

Each of these is a topic that is complex enough to warrant its own post, so for the nine Fridays I published a post to explain each one in depth.  I hope you find it engaging and informative.

Contact

Jim Handy Objective Analysis Memory Market Research +1 (408) 356-2549 Jim.Handy (at) Objective-Analysis.com

Translate to:

Website Translation GTS Translation