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How 3D NAND Shrinks ECC Requirements

Bit Errors vs. ProcessError Correction Codes, ECC, are not only important to today’s NAND flash market, but they have been a cause of concern to NAND users for a number of years.  The Memory Guy has been intending for some time to write a low-level primer on ECC, and I am finally getting it done!

Why is ECC necessary on NAND flash, yet it’s not used for other memory technologies?  The simple answer is that NAND’s purpose is to be the absolute cheapest memory on the market, and one way to achieve the lowest-possible cost is to relax the standards for data integrity — to allow bit errors every so often.  This technique has been used for a long time in both communications channels and in hard disk drives.  Data communication systems can transfer more data using less bandwidth and a weaker signal over longer distances if they use error correction to restore distorted data.  Hard disk drives can pack more bits onto a platter if the bits don’t all have to work right.  These markets (and probably certain others) have invested a lot of money in ECC research and development, and as a result ECC today  is a very well-developed science.

Denali Software published a nice Continue reading

WIOMING: Another Spin on the Hybrid Memory Cube

ST-Ericsson & CEA-Leti WIOMING Multichip ModuleAt a Conference in San Francisco today (Tuesday December 13 ) ST-Ericsson and CEA-Leti presented a paper on something the companies called a: “Breakthrough 3DIC with Wide I/O Interface.”

This product appears to be a variation on the Hybrid Memory Cube, or HMC concept detailed in a prior post.

Remember that the HMC stacks a number of DRAM chips atop a logic chip.  The memories store data and communicate to the logic chip through thousands of through-silicon vias (TSVs) while the logic chip handles communications with the outside world. Continue reading

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Jim Handy Objective Analysis Memory Market Research +1 (408) 356-2549 Jim.Handy (at) Objective-Analysis.com

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