After a big 3D XPoint launch one year ago almost anyone would expect for Intel to have had a lot of exciting new news to share about the technology at last week’s Intel Developer Forum (IDF). Those who were watching for that, though, were in for a disappointment.
For readers who don’t remember, Intel and its partner, chipmaker Micron Technology, announced a new memory layer in July 2015 that would enable in-memory databases to expand well beyond the constraints posed by standard DRAM memory. The pair also boasted the additional benefit of being nonvolatile or persistent – data would not be lost if the power failed. This technology promised to open new horizons in the world of computing.
Intel devoted a lot of effort to promotion and education during the following month’s IDF, and even demonstrated a prototype 3D XPoint SSD that performed seven to eight times as fast as Intel’s highest-performance existing NAND flash SSD – the DC S3700. Although a DIMM form factor was disclosed, no prototypes were on hand. Both were given the brand name “Optane”.
At a technical conference hosted by the IEEE this week IBM announced the results of nearly a decade of research in which its scientists have been investigating the emerging technology known as “Phase Change Memory” (PCM). The scientists presented a means of successfully storing three bits per cell for the first time, while also addressing all of PCM’s challenging idiosyncrasies, including resistance drift and temperature drift.
Commonly referred to by the erroneous nickname “TLC” for Triple Level Cell, this technology squeezes three bits of data into the space of a single bit, essentially cutting the cost per gigabyte to about one third of that of a standard memory chip making it closer in cost to flash.
With this step IBM expects to help drive a new memory layer into existence, one that will fit between the cheap and slow NAND flash used in SSDs and the fast but expensive DRAM used for main memory. Such a layer would improve the cost/performance of all types of Continue reading
The Memory Guy has recently run across a point of confusion between two very similar terms: Crossbar and Crosspoint.
A crosspoint memory is a memory where a bit cell resides at every intersection of a wordline and a bitline. It’s the smallest way you can make a memory cell. Think of the wordlines and bitlines as the wires in a window screen. If there’s a bit everywhere they cross, then it’s a crosspoint memory.
In most cases a crossbar is a communication path in a computing system. (Of course, there are exceptions, the main one being a company, Crossbar Inc., that is developing a crosspoint memory technology!) A crossbar communication path is topographically similar to a crosspoint, but its function is to connect a number of memory arrays to a number of processors. Visualize a vertical column of memory arrays named A, B, C… and a horizontal row of processors named 1, 2, 3… as is illustrated in this post’s graphic. The crossbar can connect Processor 1 to Memory A, or to any other memory that is not already connected to another processor. These connections are represented by the circles in the diagram. You can see that this is an efficient way to allow processors to share a memory space to achieve very high speed inter-processor communications.
Crossbars are quite likely to Continue reading
Micron and Intel hosted an event in San Francisco Tuesday, July 28, to introduce a new memory technology that they have named “3D XPoint”. This technology was explained to be “up to 1,000 times faster, with 1,000 times the endurance of NAND flash” while being significantly cheaper than DRAM.
Some technical details:
- 3D XPoint is a “Fundamentally Different Technology” than current memory types. It’s an ReRAM that uses material property changes for bit storage where both DRAM and NAND use charge to store a bit
- The chip currently stores 128Gb in two stacked planes of 64Gb each, storing a single bit per cell
- Today’s densest production NAND flash chips store 128GB by using MLC, so this chip actually has twice as many bit cells as any production NAND flash
- The companies do not see a clear limit to the number of planes they can stack, but are optimistic about this
- The bulk mechanism can be used to store multiple bits on a single cell (MLC)
- Today’s chip is made using a 20nm process, but can scale well past that
- There is no clear limit of how far the technology can be scaled
- It’s 1,000 times faster than NAND flash and offers 1,000 times NAND’s endurance
- It’s 10 times as dense as today’s “Conventional Memory” (which I suppose to be DRAM)
- This is not intended to replace either NAND or DRAM, but to coexist as a new memory layer between NAND and DRAM
The companies claim that other Continue reading