DDR

Why ST-MRAMs Need Specialized DDR3 Controllers

Everspin ST-MRAM press photoEverspin and Northwest Logic have just announced full interoperability between Northwest Logic’s MRAM Controller Core and Everspin Technologies’ ST-MRAM (Spin-Torque Magnetic RAM) chips. This interoperability is hardware proven on a Xilinx Virtex-7 FPGA and is now available for designs needing low-latency, high memory throughput using MRAM technology.

Since The Memory Guy knew that Everspin’s EMD3D064M ST-MRAM was fully DDR3 compatible, I had to wonder why the part would require a special controller – couldn’t it simply be controlled by any DDR3 controller?

Everspin’s product marketing director, Joe O’Hare, took the time to Continue reading

Spansion’s Super-Fast HyperFlash NOR

Comparing Spansion's HyperFlash against the speed of alternative interfacesSpansion recently introduced a NOR flash that the company boasts is the: “World’s fastest NOR flash memory”.  Named HyperFlash, the chip taps into high-speed SPI interface, doubling its width and adding a differential clock to run at an I/O rates as high as 333MB/s.

In this post’s graphic (click to enlarge) Spansion compares the HyperFlash chip’s sustained read rate (right-hand column) to that of (from left to right) asynchronous parallel NOR, single-bit SPI, industry-standard DDR Quad SPI, and Spansion’s faster rendition of DDR Quad SPI, which Spansion tells us, until now, has been the fastest flash on the market.  The company points out that HyperFlash is five times the speed of industry-standard Continue reading

A Change to Computing Architecture?

Venray's TOMI Die LayoutI got a phone call yesterday from Russell Fish of Venray Technology. He wanted to talk about how and why computer architecture is destined for a change.

I will disclose right up front that he and I were college classmates.  Even so, I will do my best to give the unbiased viewpoint that my clients expect of me.

Russell is tormented by an affliction that troubles many of us in technology: We see the direction that technology is headed, then we consider what makes sense, and we can’t tolerate any conflicts between the two.

In Russell’s case, the problem is the memory/processor speed bottleneck.

Continue reading

Contact

Jim Handy Objective Analysis Memory Market Research +1 (408) 356-2549 Jim.Handy (at) Objective-Analysis.com

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