dielectric

Micron NAND Reaches 16nm

Die Photo of Micron 16nm 128Gb NAND chipMicron has announced that it is sampling a new 128Gb NAND flash chip based upon a 16nm process, with production slated for the fourth quarter.  To The Memory Guy’s knowledge this is the tightest process available.

The company, with its partner Intel, gained a lead with its 20nm process generation through its use of a Hi-k tunnel dielectric, a new material that replaces more conventional silicon dioxide layer with a new material (Micron won’t say what) that yields the same capacitance with a thinner layer.  This has become very important with today’s tight processes because of issues of inter-cell interference.

Other NAND makers are migrating to Continue reading

SanDisk & Toshiba Move to Next Process Node

SanDisk's explanation of old vs new 19nm processesSanDisk and Toshiba, in separate announcements, both today disclosed their next-generation process technology.

The companies introduced their new “1y” processing node that, according to SanDisk, produces 19nm x 19.5nm cell, versus the earlier “19nm” process (or “1x”) that used a 19nm x 26nm cell.

The graphic for this post (click to enlarge) was presented during SanDisk’s May 5th Analyst Day and compares the 24nm process to the 19 x 26nm process, moving to the 19 x 19nm process, and eventually to “1z” which neither company is yet revealing.  After the 1z process SanDisk believes Continue reading

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Jim Handy Objective Analysis Memory Market Research +1 (408) 356-2549 Jim.Handy (at) Objective-Analysis.com

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