A lone inventor has developed a data compression algorithm that defies the theoretical “Shannon Limit“. The press hasn’t covered this recent news, even though it has dramatic implications. This is probably because the technique is so very arcane. The inventor is none other than the great-great-great granddaughter of the inventor of the tabulated punch card, Herman Hollerith.
The algorithm reduces most of the data while converting the remaining information into as many ones as possible. This not only shrinks storage requirements and costs, but in the case of flash memory, it also has an important impact on total power. Flash is erased by setting all bits to ones, and bits are written by either leaving them alone (one) or by changing them (zero). The fewer zeros in the code, the less energy required to change the bits. Energy is also saved during an erase, since fewer bits need to be brought back to the erased state.
To explain the algorithm in its simplest terms, a byte of data is evaluated. If it has more zero bits than one bits the byte is inverted and an index bit is set to reflect this fact. Next, the four bits on either side of the byte are evaluated and if one has more zeros than ones it is inverted and another index bit is set. This process continues until Continue reading
SanDisk co-founder Eli Harari was awarded the National Medal of Technology and Innovation on November 20 by President Obama. The medal, which was bestowed upon Dr. Harari in a White House ceremony, is the United States’ highest honor for scientific and technological achievement, and recognizes those whose lasting contributions have created a greater understanding of the world and improved the lives of many.
Harari co-founded SanDisk more that 25 years ago with the vision that flash memory would be used to store data in mobile products, a vision that initially took seed in photography in the 1990s, and has since become the fastest-growing Continue reading
Although the course was very well received, I never posted a link to it on The Memory Guy blog. This post is intended to correct that error.
The course runs 75 minutes and covers the basics of DRAM, non-volatile RAM, SRAM, NAND flash, NOR flash, mask ROM, and EEPROM. It explains each technology’s advances in size, cost and performance, leading up to the development of Continue reading
One of the more fun aspects of last week’s Flash Memory Summit was the presentation of the Lifetime Achievement Award. This is something that the show’s management has allowed me to do for the past four events.
This year’s award went to Dr. Simon Sze, who co-invented the floating gate transistor (the basis for all flash, EEPROM, and EPROM) at Bell Labs back in 1967.
Sze and his partner Dawon Kahng were finishing lunch in the company cafeteria with a cheesecake dessert. The two discussed what would happen if a MOSFET was built with extra layers like the layers in the cake. Their intent was to use semiconductors to replace Continue reading
I have often heard this story myself, for DRAM as well as for flash (both NAND and NOR) but I had never put in the time to test the assertion.
This statement is certainly attention grabbing, and because of that presenters everywhere will find some way to include this “fact” into their slideshows. “But is it true?” he asked me.
In a surprise announcement Toshiba has said that it will immediately cut NAND flash production by approximately 30%. The company explains that this is being done “to reduce inventory in the market and improve the overall balance between supply and demand.” Toshiba’s release implies that this move is expected to improve prices, which have dropped as low as $0.31/GB recently.
By common measures of market share, which typically leave out SanDisk (for reasons too complex to discuss here) Toshiba holds a share of roughly 30% of the NAND flash market. By cutting its output by 30% Toshiba would be reducing overall NAND supply by 10%. If we were to include SanDisk, then that percentage would decrease to about 7.5%. Either one of these is significantly more than Continue reading
Some recent news mentioned cMLC flash, which is short for “consumer MLC.” This term is used to differentiate between the cheapest available product, mainstream MLC, and products that are aimed at the computing segment, and thus carry higher price tags.
There are several of these higher-end products. Some have longer endurance, like eMLC and SLC flash. Some have faster interfaces, like ONFi and Toggle Mode. Then there are the combinations of these: a fast interface with enhanced reliability.
There are disadvantages to these. The consumer market Continue reading
The Memory Guy was a little surprised to see the advertisement in this post’s graphic. It was from an April 8 newspaper ad for Fry’s Electronics.
It’s a little early to see NAND selling for this little: The original price of $21.99 for a 32GB USB flash drive comes to $0.69/GB, and the price after the rebate of $16.99 means that the price per gigabyte of the flash is only $0.53!
At the time the lowest spot market pricing for MLC flash on the InSpectrum spot price website was $0.53, and $0.47 for TLC. According to DRAMeXchange MLC is selling for as little as $0.48.
That’s not a lot of margin for Patriot or Fry’s when you add in the cost of t Continue reading
One memory chip was so important that it was presented three times at this week’s International Solid State Circuits Conference (ISSCC) and that was the Toshiba/SanDisk 128Gb NAND flash. This chip was shown by Eli Harari in Monday’s keynote, then was featured twice in the Wednesday afternoon Nonvolatile Memories session – once by Toshiba and once by SanDisk.
The NAND chip, measuring 170.6mm², is said by both companies to be the densest NAND available. Compared to the Intel/Micron 64Gb 20nm NAND at 118mm², the device gives twice the bits in a 45% larger die area, so the companies’ claim rings true, since the only other NAND makers: Samsung and Hynix, have processes that fall far behind at 27nm and 26nm respectively.