Intel and Micron today announced that the new version of Intel’s Xeon Phi, a highly parallel coprocessor for research applications, will be built using a custom version of Micron’s Hybrid Memory Cube, or HMC.
This is only the second announced application for this new memory product – the first was a Fujitsu supercomputer back in November.
For those who, like me, were unfamiliar with the Xeon Phi, it’s a module that uses high core-count processors for problems that can be solved with high degrees of parallelism. My friend and processor guru Nathan Brookwood tells me Continue reading
Today Micron Technology announced that it is sampling the Hybrid Memory Cube (HMC) a DRAM packaging technology that it has been working on with the HMC Consortium.
Micron has been pushing to rapidly advance the HMC’s development and seems to have reached this point in an impressively brief time, given the complexity of the technology. It has only been two years since the first public appearance of the HMC at the 2011 Intel Developer Forum.
Some pretty advanced technology was used to make this product. DRAM processes are not very good at Continue reading
On Tuesday the HMC Consortium (that’s short for “Hybrid Memory Cube”) announced that members have agreed upon a specification. The consortium has been moving rapidly, meeting its targets despite the revolutionary nature of the interface.
As a reminder, this technology stacks multiple DRAMs in a single package with a logic chip at the base of the stack that performs all the signalling to the rest of the system. Signals between the DRAMs and logic chip use through-silicon vias (TSVs) as interconnections. This allows the technology to deliver 15 times the performance of DDR3 at only 30% of the power consumption. The Memory Guy first posted about the HMC in late 2011.
The consortium explains that the HMC interface already has 100 adopters, and that a few Continue reading
MOSAID announced that the company is sampling a 333GB/s 512Gb HLNAND. According to MOSAID the devices packages: “16 industry standard 32Gb NAND Flash die with two HLNAND interface devices to achieve 333MB/s output over a single byte-wide HLNAND interface channel. Conventional NAND Flash MCP designs cannot stack more than four NAND dies without suffering from performance degradation, and would require two or more channels to deliver similar throughput.”
Think of this as a lower-cost NAND version of the Hybrid Memory Cube, which packages specialized DRAM using thousands of through-silicon vias (TSVs) atop a specialized interface. Both approaches use a custom logic chip to quickly move data across a point-to-point interface with the processor.
There were a couple of surprises with this announcement: First that it was made by MOSAID even though the company was acquired by Sterling Partners late last year. It would seem that the announcement would have borne the acquirer’s name.
Second, the press all remarked that the device was innovative since it was a 16-die NAND stack. This is not new! Samsung has been shipping 16-die NAND stacks for a couple of years now. Although it’s not an economical package, it’s in production.
MOSAID first introduced the HLNAND architecture in 2007. The Memory Guy has never fully understood how HLNAND fit in with the rest of MOSAID’s business. For the most part MOSAID has become a licensor and acquirer of IP, a departure from its origins as a chip design consultancy. It is unusual (but not unheard of) for such a company to champion an industry standard and to do much R&D on its own.
Either way, this is an impressive device with compelling throughput. Here’s a wish for MOSAID to successfully create a market for this technology.
This product appears to be a variation on the Hybrid Memory Cube, or HMC concept detailed in a prior post.
Remember that the HMC stacks a number of DRAM chips atop a logic chip. The memories store data and communicate to the logic chip through thousands of through-silicon vias (TSVs) while the logic chip handles communications with the outside world. Continue reading
I got a phone call yesterday from Russell Fish of Venray Technology. He wanted to talk about how and why computer architecture is destined for a change.
I will disclose right up front that he and I were college classmates. Even so, I will do my best to give the unbiased viewpoint that my clients expect of me.
Russell is tormented by an affliction that troubles many of us in technology: We see the direction that technology is headed, then we consider what makes sense, and we can’t tolerate any conflicts between the two.
In Russell’s case, the problem is the memory/processor speed bottleneck.
In a December 1 press release IBM announced that the company will be manufacturing Micron Technology’s Hybrid Memory Cube (HMC) which IBM claims to be “the first commercial CMOS manufacturing technology to employ through-silicon vias (TSVs).”
This device is one that Altera, Intel, Micron, Open Silicon, Samsung, and Xilinx have all presented recently as a plausible solution to the difficulty of increasing the speed of DRAM/processor communications. The Hybrid Memory Cube Consortium (HMCC) website offers a deep dive into the details of the consortium and the technology.