IBM

Extending the Write/Erase Lifetime of Phase Change Memory: Part 3 – Failure Modes for the Threshold Switch

Ron NealeThis is Part 3 of a short Memory Guy series which continues to explore the possible future impact on PCM memory performance, especially write/erase endurance, building on the results of the IBM/Yale University analysis outlined in Part 1 and Part 2.


Part 3 of this series of articles triggered by the recently published PCM device analysis by a team from IBM/Yale University, moves to a look at its possible implications for the arsenic doped GST threshold switch.  Although the threshold switch was not part of the IBM/Yale work, the implementation of the call for bipolar operation of PCMs means there will be a requirement for a threshold switch whose durability matches that of the memory with which it will be associated in a memory array.

If the study’s finding for PCM can be applied to the arsenic-doped GST threshold switch which is used in today’s commercially-available PCM arrays then the threshold switch might just be the weak link that accounts for the poor endurance of commercial PCM memory arrays.

One little conundrum we must address is: Which Continue reading

Storage/Memory Hierarchy 40 Years Ago

1978 Memory/Storage HierarchyLast year I stumbled upon something on the Internet that I thought would be fun to share.  It’s the picture on the left from a 1978 book by Laurence Allman: Memory Design Microcomputers to Mainframes.  The picture’s not too clear, but it is a predecessor to a graphic of the memory/storage hierarchy that The Memory Guy often uses to explain how various elements (HDD, SSD, DRAM) fit together.

On the horizontal axis is Access Time, which the storage community calls latency.  The vertical axis shows cost per bit.  The chart uses a log-log format: both the X and Y axes are in orders of magnitude.  This allows a straight line to be drawn through the points that represent the various technologies, and prevent most of the technologies from being squeezed into the bottom left corner of the chart.

What I find fascinating about this graphic is not only the technologies that it includes but also the way that it’s presented.  First, let’s talk about the technologies.

At the very top we have RAM: “TTL, ECL, and fast MOS static types.”  TTL and ECL, technologies that are seldom Continue reading

What Memory Will Intel’s Purley Platform Use?

Part of Intel Purley SlideThere has been quite a lot of interest over the past few days about the apparently-inadvertent disclosure by Intel of its server platform roadmap.  Detailed coverage in The Platform showed a couple of slides with key memory information for the upcoming Purley server platform which will support the Xeon “Skylake” processor family.  (A review of this post on 7/13/17 revealed that The Platform’s website has disappeared.  The above link and the next one no longer work.)

One slide, titled: “Purley: Biggest Platform Advancement Since Nehalem” includes this post’s graphic, which tells of a memory with: “Up to 4x the capacity & lower cost than DRAM, and 500x faster than NAND.”

The Memory Guy puzzled a bit about what this might be.  The only memory chip technology today with a cost structure lower than that of DRAM is NAND flash, and there is unlikely to be any technology within the leaked roadmap’s 2015-2017 time span that will change that.  MRAM, ReRAM, PCM, FRAM, and other technologies can’t beat DRAM’s cost, and will probably take close to a decade to get to that point.

Since that’s the case, then what is this mystery memory?  If we think of Continue reading

DRAM Inventor Wins Kyoto Prize

Dr. Robert Dennard Receiving the Kyoto Advanced Technology Prize.  Source: The Inamori FoundationThis year’s Kyoto Prizes included an Advanced Technology Prize for the father of DRAM, IBM’s Dr. Robert Dennard.

The Kyoto Prize, one of the world’s most prestigious accolades, is an international award bestowed once a year by The Inamori Foundation to honor those who have contributed significantly to the scientific, cultural and spiritual betterment of humankind.  Some say it is similar to the Nobel Prize, and seven Kyoto Prize laureates have gone on to win the Nobel Prize.

In addition to the kudos of receiving this honor, Denning was also Continue reading

An Alternative Kind of Vertical 3D NAND String

Samsung's TCAT 3D NAND flashMy prior 3D NAND post explained how Toshiba’s BiCS cell works, using a silicon nitride charge trap to substitute for a floating gate.  This post will look at an alternative technology used by Samsung and Hynix which is illustrated in the first graphic, a diagram Samsung presented at a technical conference. This cell also uses a charge trap.

Let The Memory Guy warn you, if the process in my prior post seemed tricky, this one promises to put that one to shame!

Part of this stems from the use of a different kind of NAND bit cell.  You can shrink flash cells smaller if you use a high-k gate dielectric (one with a high dielectric constant “k”) since it Continue reading

3D NAND: Making a Vertical String

Toshiba's Original BiCS Diagram - IEDM 2007Let’s look at how one form of 3D NAND is manufactured.  For this post we will explore the original design suggested by Toshiba at the IEEE’s International Electron Device Meeting (IEDM) in 2007.  It’s shown in the first graphic of this post.  (Click on any of the graphics for a better view.)

Toshiba calls this technology “BiCS” for “Bit Cost Scaling.”  The technique doesn’t scale the process the way the world of semiconductors has always done to date – it scales the cost without shrinking the length and width of the memory cell.  It accomplishes this by going vertically, as is shown in this post’s first graphic.

This takes a special effort. This is where the real Continue reading

Samsung DRAMs in Massive Leibniz SuperMUC

The Leibniz Supercomputing Centre's SuperMUC supercomputerToday Samsung announced that its chips are used exclusively to make up the 324-terabytes of DRAM in Germany’s new Leibniz Supercomputing Centre SuperMUC supercomputer.

Samsung’s release tells us that the SuperMUC, the most powerful supercomputer system in Europe, is an IBM System x iDataPlex dx360 M4 server built using over 18,000 Intel Xeon CPUs and over 80,000 4GB DRAM modules from Samsung.  (Simple math makes this out to be 82,944 modules.)

That looks like a lot of silicon!  Let’s see how much that might be.

A 4GB parity DRAM module would use nine 4Gb DRAM chips, which Samsung appears to Continue reading

IBM to Build Micron Hybrid Memory Cube

Conceptual Cutaway Drawing of the Hybrid Memory CubeIn a December 1 press release IBM announced that the company will be manufacturing Micron Technology’s Hybrid Memory Cube (HMC) which IBM claims to be “the first commercial CMOS manufacturing technology to employ through-silicon vias (TSVs).”

This device is one that Altera, Intel, Micron, Open Silicon, Samsung, and Xilinx have all presented recently as a plausible solution to the difficulty of increasing the speed of DRAM/processor communications.  The Hybrid Memory Cube Consortium (HMCC) website offers a deep dive into the details of the consortium and the technology.

Continue reading

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Jim Handy Objective Analysis Memory Market Research +1 (408) 356-2549 Jim.Handy (at) Objective-Analysis.com

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