There has been quite a lot of interest over the past few days about the apparently-inadvertent disclosure by Intel of its server platform roadmap. Detailed coverage in The Platform showed a couple of slides with key memory information for the upcoming Purley server platform which will support the Xeon “Skylake” processor family.
One slide, titled: “Purley: Biggest Platform Advancement Since Nehalem” includes this post’s graphic, which tells of a memory with: “Up to 4x the capacity & lower cost than DRAM, and 500x faster than NAND.”
The Memory Guy puzzled a bit about what this might be. The only memory chip technology today with a cost structure lower than that of DRAM is NAND flash, and there is unlikely to be any technology within the leaked roadmap’s 2015-2017 time span that will change that. MRAM, ReRAM, PCM, FRAM, and other technologies can’t beat DRAM’s cost, and will probably take close to a decade to get to that point.
Since that’s the case, then what is this mystery memory? If we think of memory systems, rather than memory chips we can come up with one very plausible answer. Intel may be very Continue reading
The Kyoto Prize, one of the world’s most prestigious accolades, is an international award bestowed once a year by The Inamori Foundation to honor those who have contributed significantly to the scientific, cultural and spiritual betterment of humankind. Some say it is similar to the Nobel Prize, and seven Kyoto Prize laureates have gone on to win the Nobel Prize.
In addition to the kudos of receiving this honor, Denning was also Continue reading
My prior 3D NAND post explained how Toshiba’s BiCS cell works, using a silicon nitride charge trap to substitute for a floating gate. This post will look at an alternative technology used by Samsung and Hynix which is illustrated in the first graphic, a diagram Samsung presented at a technical conference. This cell also uses a charge trap.
Let The Memory Guy warn you, if the process in my prior post seemed tricky, this one promises to put that one to shame!
Part of this stems from the use of a different kind of NAND bit cell. You can shrink flash cells smaller if you use a high-k gate dielectric (one with a high dielectric constant “k”) since it Continue reading
Let’s look at how one form of 3D NAND is manufactured. For this post we will explore the original design suggested by Toshiba at the IEEE’s International Electron Device Meeting (IEDM) in 2007. It’s shown in the first graphic of this post. (Click on any of the graphics for a better view.)
Toshiba calls this technology “BiCS” for “Bit Cost Scaling.” The technique doesn’t scale the process the way the world of semiconductors has always done to date – it scales the cost without shrinking the length and width of the memory cell. It accomplishes this by going vertically, as is shown in this post’s first graphic.
This takes a special effort. This is where the real Continue reading
Samsung’s release tells us that the SuperMUC, the most powerful supercomputer system in Europe, is an IBM System x iDataPlex dx360 M4 server built using over 18,000 Intel Xeon CPUs and over 80,000 4GB DRAM modules from Samsung. (Simple math makes this out to be 82,944 modules.)
That looks like a lot of silicon! Let’s see how much that might be.
A 4GB parity DRAM module would use nine 4Gb DRAM chips, which Samsung appears to Continue reading
In a December 1 press release IBM announced that the company will be manufacturing Micron Technology’s Hybrid Memory Cube (HMC) which IBM claims to be “the first commercial CMOS manufacturing technology to employ through-silicon vias (TSVs).”
This device is one that Altera, Intel, Micron, Open Silicon, Samsung, and Xilinx have all presented recently as a plausible solution to the difficulty of increasing the speed of DRAM/processor communications. The Hybrid Memory Cube Consortium (HMCC) website offers a deep dive into the details of the consortium and the technology.