In a word: No.
(Before I get too far into this allow me to admit that The Memory Guy doesn’t understand quantum physics, so I will be presenting this only to the depth that I understand it. There will be no band-gap diagrams or equations to wrestle with.)
Both 3D NAND and planar NAND use Fowler Nordheim Tunneling (FN) to both program and erase. This differs from NOR flash which programs bits using Continue reading
One of the thornier problems in making 3D NAND is the job of connecting the peripheral logic (the row decoders) to all of those control gates that are on layers buried somewhere within the bit array. Remember that the control gates are the conductive sheets of polysilicon or tantalum nitride at various depths in the chip.
The problem boils down to this: You can’t run connections from each layer up or down the side of the chip to get to the CMOS circuits below. Instead you have to create a terrace structure to expose and connect to each layer.
These connections are made by etching a stair-step pattern into the layers and sinking Continue reading
My prior 3D NAND post explained how Toshiba’s BiCS cell works, using a silicon nitride charge trap to substitute for a floating gate. This post will look at an alternative technology used by Samsung and Hynix which is illustrated in the first graphic, a diagram Samsung presented at a technical conference. This cell also uses a charge trap.
Let The Memory Guy warn you, if the process in my prior post seemed tricky, this one promises to put that one to shame!
Part of this stems from the use of a different kind of NAND bit cell. You can shrink flash cells smaller if you use a high-k gate dielectric (one with a high dielectric constant “k”) since it Continue reading
Let’s look at how one form of 3D NAND is manufactured. For this post we will explore the original design suggested by Toshiba at the IEEE’s International Electron Device Meeting (IEDM) in 2007. It’s shown in the first graphic of this post. (Click on any of the graphics for a better view.)
Toshiba calls this technology “BiCS” for “Bit Cost Scaling.” The technique doesn’t scale the process the way the world of semiconductors has always done to date – it scales the cost without shrinking the length and width of the memory cell. It accomplishes this by going vertically, as is shown in this post’s first graphic.
This takes a special effort. This is where the real Continue reading
In August 2013 Samsung announced its V-NAND, the first production 3D NAND, kicking off a big change in the way that NAND flash will be manufactured. This new technology raises a number of important questions:
- What exactly is a 3D NAND?
- Why does the industry need to go to a 3D topology?
- How the heck do they make such a product?
To answer these questions I assembled a series of articles posted as weekly segments on The Memory Guy blog during the fourth quarter of 2013. The different sections are listed below, with hot links to each section.
- Why Do We Need 3D NAND?
- What Is a 3D NAND?
- Making a Vertical NAND String
- An Alternative Kind of Vertical 3D NAND String
- How Do You Access the Control Gates?
- Benefits of Charge Traps over Floating Gates
- How Do You Erase and Program 3D NAND?
- 3D NAND’s Impact on the Equipment Market
- Who Will Make It and When?
Each of these is a topic that is complex enough to warrant its own post, so for the nine Fridays I published a post to explain each one in depth. I hope you find it engaging and informative.
Micron has announced that it is sampling a new 128Gb NAND flash chip based upon a 16nm process, with production slated for the fourth quarter. To The Memory Guy’s knowledge this is the tightest process available.
The company, with its partner Intel, gained a lead with its 20nm process generation through its use of a Hi-k tunnel dielectric, a new material that replaces more conventional silicon dioxide layer with a new material (Micron won’t say what) that yields the same capacitance with a thinner layer. This has become very important with today’s tight processes because of issues of inter-cell interference.
Other NAND makers are migrating to Continue reading
The companies introduced their new “1y” processing node that, according to SanDisk, produces 19nm x 19.5nm cell, versus the earlier “19nm” process (or “1x”) that used a 19nm x 26nm cell.
The graphic for this post (click to enlarge) was presented during SanDisk’s May 5th Analyst Day and compares the 24nm process to the 19 x 26nm process, moving to the 19 x 19nm process, and eventually to “1z” which neither company is yet revealing. After the 1z process SanDisk believes Continue reading
Every so often I run into someone who asks about the discrepancy between various analysts’ NAND market share rankings and SanDisk’s shipments. After all, SanDisk is a leading producer of flash memory and has captive manufacture through its joint venture with Toshiba. Yet, most market share rankings leave SanDisk out.
What’s going on here?
Owing to a long-standing convention SanDisk’s NAND chips aren’t counted since they are sold as “Systems” (with a controller.) The World Semiconductor Trade Statistics (WSTS) set that rule up, and most analysts Continue reading
The trade press has recently carried reports of a NAND shortage which The Memory Guy finds to be very premature. True, NAND prices are not at their lowest point – today NAND can be found for 38 cents per gigabyte, up from a low of 31 cents in July. But does this constitute a shortage? No, not really.
One of the key indicators of a shortage is a crossover between spot and contract pricing – during an oversupply spot pricing is lower than contract pricing since OEMs and suppliers both place excess product on the market and compete on price. During a shortage the opposite is true – suppliers don’t have any Continue reading
As this post’s graphic illustrates the company has has seen downward-trending memory revenues for five of the past six quarters, but Q2 revenues increased by ten percent. Interestingly enough, the last quarter-to-quarter increase was a miniscule 0.3% one in Q2 of 2011. It looks as if growth tends to regularly occur in Samsung’s second quarter.
Last quarter’s revenue growth helps to debunk rumors that Samsung was Continue reading