Intel to Use Micron Hybrid Memory Cube

Micron: "Bursting Through The Memory Wall"Intel and Micron today announced that the new version of Intel’s Xeon Phi, a highly parallel coprocessor for research applications, will be built using a custom version of Micron’s Hybrid Memory Cube, or HMC.

This is only the second announced application for this new memory product – the first was a Fujitsu supercomputer back in November.

For those who, like me, were unfamiliar with the Xeon Phi, it’s a module that uses high core-count processors for problems that can be solved with high degrees of parallelism.  My friend and processor guru Nathan Brookwood tells me Continue reading

Comparing Samsung V-NAND to Micron 16nm Planar NAND

Andrew Walker, SchiltronI was recently directed to a very interesting blog post written by 3D technologist Andrew Walker of Schiltron in which he compares two NAND flash chips that were presented at the IEEE International Solid State Circuits Conference (ISSCC) on February 12.

The post, titled Samsung’s V-NAND Flash at the 2014 ISSCC: Ye Distant Spires… is on the 3D InCites website.

Dr. Walker puts a lot more time and effort into his graphic representations of 3D NAND chips than do others (The Memory Guy included) and this makes it much easier to understand the issues he points out.  He shows us that Samsung’s 3D NAND cell is about 5 times the size of a 40nm planar NAND cell and about 30 times that of Micron’s 16nm planar cell, and that the 3D NAND’s physical area is unlikely to change with any future 3D technology generations.

For this and other reasons (given in the article) he states that the Samsung V-NAND is “an impressive achievement but not a realistic foundation for the future.”

After having compiled my series on 3D NAND I can appreciate Dr. Walker’s opinion.  This is certainly going to be a difficult technology to master, and it could be quite some time before the cost structure for 3D NAND can compete against that of today’s planar technologies.

Give the Walker post a quick read and judge for yourself whether we are at the brink of a 3D conversion or if this technology can be expected to slip out a few years.

Why NAND is So Difficult to Scale

ASML chart chowing the lithography used for 4X, 3X, 2X, and 1Xnm planar NAND and 3D NANDNAND flash is the process leader in memory technology, and this puts it in a very challenging position: It must ramp to high volume production using techniques that have never been tried before.

The graphic for this post (click to enlarge), supplied by ASML, the semiconductor industry’s leading lithography tool supplier, illustrates the challenge of migrating from one process node to the next.  Across the bottom, on the X-axis, are representative process nodes ranging from “2D-45”, or two-dimensional (planar) 45nm NAND, to “3D-5x”, or three-dimensional 5xnm NAND.  Below these numbers are the year of volume production.

The vertical axis, labeled “Tolerance” represents the minimum Continue reading

Did SK hynix Beat Samsung to the 8Gb LPDDR4?

SK hynix (top) and Samsung (bottom) 8Gb 20nm-class LPDDR4Every so often something very strange happens that puzzles The Memory Guy.  On December 29 (or Dec. 30 in Seoul) something odd occurred.

I received two e-mails, one from SK hynix at 3:55 PM Pacific Time, and one from Samsung exactly one hour later.  Both were press releases.

The SK hynix release was titled: “SK Hynix Developed the World’s First Next Generation Mobile Memory LPDDR4”.  It announced that the company is sampling its 20nm-class 8Gb LPDDR4 DRAM to customers.

The Samsung release was Continue reading

3D NAND: Who Will Make It and When?

SK hynix 3D NAND Cross SectionThis series has looked at 3D NAND technology in a good deal of technical depth.  The last question to be answered centers around the players and the timing of the technology.  A lot has been said about the technology and its necessity.  Will everyone be making 3D NAND?  When will this big transition occur?

This post will provide an update as of its publication (13 December 2013) to show each company’s current status, to the best of The Memory Guy’s understanding.  Readers may want to refer back to the earlier posts in this series, as well as to a June 2013 Nikkei TechON article that gives a good review of the 3D NAND alternatives that have been presented at various technical conferences.

Let’s start with Samsung, the largest producer of NAND flash today.  Just prior to Memcon 2013 last Continue reading

Rambus and Micron Sign License Agreement

The following is excerpted from an Objective Analysis Alert that can be downloaded from the company’s website.

Micron Licenses Rambus IPRambus and Micron announced on Tuesday that they have signed a patent cross license agreement.  Micron receives rights to Rambus IC patents, including memories.  Both Micron and Elpida products will be covered.  The companies have thus settled all outstanding patent and antitrust claims in their 13-year court battle.

Micron will make royalty payments to Rambus of up to $10 million per quarter over the next seven years, totaling $280 million, after which Micron will receive a perpetual, paid-up license.

Rambus and Micron both have Continue reading

How Do You Erase and Program 3D NAND?

How FN Tunneling WorksSome of my readers have asked: “How is 3D NAND programmed and erased?  Is it any different from planar NAND?”

In a word: No.

(Before I get too far into this allow me to admit that The Memory Guy doesn’t understand quantum physics, so I will be presenting this only to the depth that I understand it.  There will be no band-gap diagrams or equations to wrestle with.)

Both 3D NAND and planar NAND use Fowler Nordheim Tunneling (FN) to both program and erase.  This differs from NOR flash which programs bits using Continue reading

3D NAND: How do You Access the Control Gates?

Samsung's TCAT NAND Flash Wordline COnnectionsOne of the thornier problems in making 3D NAND is the job of connecting the peripheral logic (the row decoders) to all of those control gates that are on layers buried somewhere within the bit array.  Remember that the control gates are the conductive sheets of polysilicon or tantalum nitride at various depths in the chip.

The problem boils down to this: You can’t run connections from each layer up or down the side of the chip to get to the CMOS circuits below.  Instead you have to create a terrace structure to expose and connect to each layer.

These connections are made by etching a stair-step pattern into the layers and sinking Continue reading

An Alternative Kind of Vertical 3D NAND String

Samsung's TCAT 3D NAND flashMy prior 3D NAND post explained how Toshiba’s BiCS cell works, using a silicon nitride charge trap to substitute for a floating gate.  This post will look at an alternative technology used by Samsung and Hynix which is illustrated in the first graphic, a diagram Samsung presented at a technical conference. This cell also uses a charge trap.

Let The Memory Guy warn you, if the process in my prior post seemed tricky, this one promises to put that one to shame!

Part of this stems from the use of a different kind of NAND bit cell.  You can shrink flash cells smaller if you use a high-k gate dielectric (one with a high dielectric constant “k”) since it Continue reading

3D NAND: Making a Vertical String

Toshiba's Original BiCS Diagram - IEDM 2007Let’s look at how one form of 3D NAND is manufactured.  For this post we will explore the original design suggested by Toshiba at the IEEE’s International Electron Device Meeting (IEDM) in 2007.  It’s shown in the first graphic of this post.  (Click on any of the graphics for a better view.)

Toshiba calls this technology “BiCS” for “Bit Cost Scaling.”  The technique doesn’t scale the process the way the world of semiconductors has always done to date – it scales the cost without shrinking the length and width of the memory cell.  It accomplishes this by going vertically, as is shown in this post’s first graphic.

This takes a special effort. This is where the real Continue reading


Jim Handy Objective Analysis Memory Market Research +1 (408) 356-2549 Jim.Handy (at) Objective-Analysis.com

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