At a technical conference hosted by the IEEE this week IBM announced the results of nearly a decade of research in which its scientists have been investigating the emerging technology known as “Phase Change Memory” (PCM). The scientists presented a means of successfully storing three bits per cell for the first time, while also addressing all of PCM’s challenging idiosyncrasies, including resistance drift and temperature drift.
Commonly referred to by the erroneous nickname “TLC” for Triple Level Cell, this technology squeezes three bits of data into the space of a single bit, essentially cutting the cost per gigabyte to about one third of that of a standard memory chip making it closer in cost to flash.
With this step IBM expects to help drive a new memory layer into existence, one that will fit between the cheap and slow NAND flash used in SSDs and the fast but expensive DRAM used for main memory. Such a layer would improve the cost/performance of all types of Continue reading
Although the course was very well received, I never posted a link to it on The Memory Guy blog. This post is intended to correct that error.
The course runs 75 minutes and covers the basics of DRAM, non-volatile RAM, SRAM, NAND flash, NOR flash, mask ROM, and EEPROM. It explains each technology’s advances in size, cost and performance, leading up to the development of Continue reading
In brief: Macronix’ researchers buried a heater in the array to heat the tunnel dielectric, annealing out the disruptions & traps that might cause a bit to fail.
A prototype has so far been tested more than 100 million cycles and it shows no sign of impending failure. Researchers believe that it is likely to reach one billion or more cycles, but such testing will take several months. This just may be able to Continue reading
Lane Mason of Objective Analysis recently shared with The Memory Guy an article he wrote for the 4 April 2007 Denali Memory Report covering Phase Change Memory (PCM or PRAM.) It looked like something big was about to happen with the technology: PCM looked nearly ready to enter production.
Here it is 2012, and PCM represents little more than a drop in the bucket when it comes to memory sales, although Continue reading
After years of prototyping Micron Technology claims to be the first to introduce production volumes of Phase-Change Memory, or PCM. This memory, also known as PRAM, has long been positioned as a contender to replace flash once flash reaches its scaling limit. Rather than use electrons to store a bit, PCM uses a type of glass that is conductive when in a crystalline state and resistive when amorphous, two states that are relatively easy to control. The size of the bits can shrink to a very small dimensions, allowing PCM to scale into the single-digit number of nanometers, which most folks today believe to be beyond the realm of flash.
This product began its life at Intel, then followed the Numonyx spin-off, and was taken over by Micron when it acquired Numonyx. In fact, Intel got into PCM very early on – this post’s graphic is the cover of an Electronics Magazine from September 1970 with an Intel story, written by Gordon Moore, telling about a 128-bit PCM research chip.
So far only three companies have produced samples Continue reading
An acquaintance recently brought to my attention an article in R&D Magazine about some pioneering research on phase-change memories or PCM. The researchers’ findings hold a lot of promise. (R&D Magazine’s article is based upon an original paper in the journal Science.)
A team led by Ritesh Agarwal, associate professor at the University of Pennsylvania, was trying to develop a better understanding of the mechanism behind the phase changes in PCM. The team found that existing programming algorithms that involve melting the material could be replaced with pulses of electrical current that not only would program the cell without heat, but provided an “On” to “Off” resistance ratio of 2-3 orders of magnitude, which renders the cell significantly easier to read, especially in the presence of noise. This effectively makes memory chip design Continue reading
Everyone knows that flash memory is about to hit its scaling limit – it’s right around the corner. We’re ready for it because it’s been right around the corner for more than a decade now. It’s so close we can taste it.
When will it happen?
One thing that is quite clear is that nobody knows when NAND flash will stop scaling. Everyone knows that it’s soon, but researchers continue to find ways to push the technology another couple of process nodes past where anyone thought it could possibly go, and they have been doing this since Continue reading
The IEEE Spectrum published an interesting article postulating that Russia’s recently-failed Mars probe may have suffered from bad memory chips. According to the Spectrum article the Russian government’s Official Accident Investigation Results faulted SRAMs:
The report blames the loss of the probe on memory chips that became fatally damaged by cosmic rays.
Both the main computer and the backup computer seem to have failed at the same time, Continue reading
Since ISSCC is a conference at which you meet the best and brightest minds in the industry it should come as no surprise that I was able to meet with several of the most forward-thinking industry luminaries. One of them explained to me a very fundamental difficulty with resistive RAMs (ReRAMs): These devices require a forward current to be programmed to a “1” and a reverse current to be set to a zero. This goes against the ideal crosspoint memory design in which a bit would consist of nothing more than a diode in series with a memory element. By inserting a diode, the current can only run in one direction, so a bit can be programmed or it can be erased, but not both.