Racetrack

Storage/Memory Hierarchy 40 Years Ago

1978 Memory/Storage HierarchyLast year I stumbled upon something on the Internet that I thought would be fun to share.  It’s the picture on the left from a 1978 book by Laurence Allman: Memory Design Microcomputers to Mainframes.  The picture’s not too clear, but it is a predecessor to a graphic of the memory/storage hierarchy that The Memory Guy often uses to explain how various elements (HDD, SSD, DRAM) fit together.

On the horizontal axis is Access Time, which the storage community calls latency.  The vertical axis shows cost per bit.  The chart uses a log-log format: both the X and Y axes are in orders of magnitude.  This allows a straight line to be drawn through the points that represent the various technologies, and prevent most of the technologies from being squeezed into the bottom left corner of the chart.

What I find fascinating about this graphic is not only the technologies that it includes but also the way that it’s presented.  First, let’s talk about the technologies.

At the very top we have RAM: “TTL, ECL, and fast MOS static types.”  TTL and ECL, technologies that are seldom Continue reading

Fundamentals of Memory – Free Online Course

Fundamentals of Memory Course - EE TimesSome time ago The Memory Guy was asked by Numonyx (later acquired by Micron) to put together an online course for EE Times on memory technologies, explaining how each one works and where it is used.

Although the course was very well received, I never posted a link to it on The Memory Guy blog.  This post is intended to correct that error.

The course runs 75 minutes and covers the basics of DRAM, non-volatile RAM, SRAM, NAND flash, NOR flash, mask ROM, and EEPROM.  It explains each technology’s advances in size, cost and performance, leading up to the development of Continue reading

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Jim Handy Objective Analysis Memory Market Research +1 (408) 356-2549 Jim.Handy (at) Objective-Analysis.com

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