In a move touted as a merger of equals, Cypress will acquire Spansion in an all-stock transaction slated to close in the second quarter of 2015. The purchase price is estimated at $1.6 billion.
Cypress points out that it is the leading producer of SRAMs, and that Spansion is the leading NOR flash provider.
One striking feature of this transaction is the Continue reading
Spansion recently introduced a NOR flash that the company boasts is the: “World’s fastest NOR flash memory”. Named HyperFlash, the chip taps into high-speed SPI interface, doubling its width and adding a differential clock to run at an I/O rates as high as 333MB/s.
In this post’s graphic (click to enlarge) Spansion compares the HyperFlash chip’s sustained read rate (right-hand column) to that of (from left to right) asynchronous parallel NOR, single-bit SPI, industry-standard DDR Quad SPI, and Spansion’s faster rendition of DDR Quad SPI, which Spansion tells us, until now, has been the fastest flash on the market. The company points out that HyperFlash is five times the speed of industry-standard Continue reading
In a word: No.
(Before I get too far into this allow me to admit that The Memory Guy doesn’t understand quantum physics, so I will be presenting this only to the depth that I understand it. There will be no band-gap diagrams or equations to wrestle with.)
Both 3D NAND and planar NAND use Fowler Nordheim Tunneling (FN) to both program and erase. This differs from NOR flash which programs bits using Continue reading
A prior post in this series (3D NAND: Making a Vertical String) discussed the difficulties of successfully manufacturing a charge trap flash bit. Still, Spansion, and now other flash makers, have determined to take this route. Why is that?
In Spansion’s case, a charge trap was a means of doubling the bit capacity of its products. It was an inexpensive alternative to standard MLC flash. To date this strategy has worked very well.
As mentioned in that earlier post, 3D NAND uses a charge trap because it’s extremely difficult to create features, like a floating gate, sideways – lithography works from the top down. A charge trap, when used to replace a floating gate, doesn’t need to be patterned, since the Continue reading
Let’s look at how one form of 3D NAND is manufactured. For this post we will explore the original design suggested by Toshiba at the IEEE’s International Electron Device Meeting (IEDM) in 2007. It’s shown in the first graphic of this post. (Click on any of the graphics for a better view.)
Toshiba calls this technology “BiCS” for “Bit Cost Scaling.” The technique doesn’t scale the process the way the world of semiconductors has always done to date – it scales the cost without shrinking the length and width of the memory cell. It accomplishes this by going vertically, as is shown in this post’s first graphic.
This takes a special effort. This is where the real Continue reading
At the Flash Memory Summit yesterday ES Jung, PhD, EVP & GM for the Samsung R&D Center, explained the inner workings of Samsung’s new V-NAND vertical NAND flash technology. I will shortly be writing a series to explain what a 3D NAND is since there is little on the web that gives clear details about the technology.
One key attribute of most 3D NAND approaches is the use of a charge trapping layer. This has to do with the difficulty of manufacturing sideways floating gates.
Dr Jung delighted the show’s audience by explaining that a standard floating gate is like Continue reading
Just in case anyone thought that NOR flash was not going to get any denser, Spansion announced a single-chip 8Gb parallel NOR today. This product, built using Spansion’s MirrorBit technology on a 45nm line is not only the densest monolithic NOR chip on the market, it’s also the NOR flash with the finest process technology.
Spansion’s GL-T product is aimed at applications that need high densities at read speeds faster than those that NAND flash can deliver. Spansion tells The Memory Guy that read performance is 95MB/s and program performance is 1.8 MB/s.
Sampling will commence in December, with production in the first quarter of 2013.
Today I saw an announcement from another market research firm about a new report with flash memory market shares for 2011. I found it remarkable that the way these chips are counted varies enough that the company decided to openly discuss this issue right in the press release for the report!
Memory market statistics are compiled by numerous firms: The World Semiconductor Trade Statistics (WSTS) sold in the US and Europe by the Semiconductor Industry Association (SIA), Gartner Dataquest, IHS iSuppli, Web Feet, Semico, Forward Insights, and even DRAMexchange. Lots of entities use conflicting definitions of what is and what is not a chip. This causes each company’s numbers to differ from the others’.
In the case of WSTS, a chip that is packaged with another chip into a board becomes Continue reading
SK Hynix and Spansion have announced a strategic NAND alliance under which Hynix will serve as a foundry for low-density SLC NAND chips made for Spansion using Hynix’ advanced processing nodes.
These products, aimed at the embedded market, should serve to strengthen Spansion in a market in which the company thrives. In fact, Spansion expressed this very well in their press release, citing: “Spansion’s recognized customer support and commitment for longevity of supply, which is highly valued in the embedded market, where Spansion has established relationships.”
The new chips will be manufactured in “4x, 3x, and 2xnm” process technologies.
The companies have also agreed to cross-license their patent portfolios.
You may be asking yourself: “What does Hynix Continue reading