Everspin and Northwest Logic have just announced full interoperability between Northwest Logic’s MRAM Controller Core and Everspin Technologies’ ST-MRAM (Spin-Torque Magnetic RAM) chips. This interoperability is hardware proven on a Xilinx Virtex-7 FPGA and is now available for designs needing low-latency, high memory throughput using MRAM technology.
Since The Memory Guy knew that Everspin’s EMD3D064M ST-MRAM was fully DDR3 compatible, I had to wonder why the part would require a special controller – couldn’t it simply be controlled by any DDR3 controller?
Everspin’s product marketing director, Joe O’Hare, took the time to Continue reading
For the past decade or so memory researchers have been looking to Spin Transfer Torque (sometimes called “Spin Torque Transfer”) MRAMs as a way of getting to tighter processes than conventional toggle MRAM. It seems that current densities in toggle MRAM rise too high as the process shrinks – at some point the process could no longer scale since chips would burn themselves out during programming. The ST-RAM paves Everspin’s path toward Continue reading
The IEEE Spectrum published an interesting article postulating that Russia’s recently-failed Mars probe may have suffered from bad memory chips. According to the Spectrum article the Russian government’s Official Accident Investigation Results faulted SRAMs:
The report blames the loss of the probe on memory chips that became fatally damaged by cosmic rays.
Both the main computer and the backup computer seem to have failed at the same time, Continue reading