Toshiba

3D NAND: Who Will Make It and When?

SK hynix 3D NAND Cross SectionThis series has looked at 3D NAND technology in a good deal of technical depth.  The last question to be answered centers around the players and the timing of the technology.  A lot has been said about the technology and its necessity.  Will everyone be making 3D NAND?  When will this big transition occur?

This post will provide an update as of its publication (13 December 2013) to show each company’s current status, to the best of The Memory Guy’s understanding.  Readers may want to refer back to the earlier posts in this series, as well as to a June 2013 Nikkei TechON article that gives a good review of the 3D NAND alternatives that have been presented at various technical conferences.

Let’s start with Samsung, the largest producer of NAND flash today.  Just prior to Memcon 2013 last Continue reading

3D NAND’s Impact on the Equipment Market

Costs to Migrate to Next Lithography Node - Applied Materials (click to enlarge)A very unusual side effect of the move to 3D NAND will be the impact on the equipment market.  3D NAND takes the pressure off of lithographic steps and focuses more attention on deposition and etch.  The reason for going to 3D is that it provides a path to higher density memories without requiring lithographic shrinks.

This sounds like bad news for stepper makers like ASML, Canon, and Nikon while it should be a boon to deposition and etch equipment makers like Applied Materials, Tokyo Electron, and Lam Research.

In its summer 2013 V-NAND announcement, Samsung explained that it would be Continue reading

How Do You Erase and Program 3D NAND?

How FN Tunneling WorksSome of my readers have asked: “How is 3D NAND programmed and erased?  Is it any different from planar NAND?”

In a word: No.

(Before I get too far into this allow me to admit that The Memory Guy doesn’t understand quantum physics, so I will be presenting this only to the depth that I understand it.  There will be no band-gap diagrams or equations to wrestle with.)

Both 3D NAND and planar NAND use Fowler Nordheim Tunneling (FN) to both program and erase.  This differs from NOR flash which programs bits using Continue reading

The Father of Flash Memory

Dr. Fujio Masuoka, the inventor of NAND and NOR flash memoryAt the Flash Memory Summit in August I had the honor of awarding Fujio Masuoka, the inventor of both NAND and NOR flash, the Flash Memory Summit Lifetime Achievement Award.  This award is given to the giants of the flash memory industry to acknowledge their contributions.

Dr. Masuoka first described NOR flash at the 1984 International Electron Device Meeting (IEDM) in San Francisco, and NAND flash at the same venue in 1987.  His paper “A new flash EEPROM cell using triple polysilicon technology” introduced a technology that is now used everywhere.

The award has also been given to Intel’s Flash team who brought the first commercial products to the market, and SanDisk co-founder Eli Harari, for devising a way to manufacture a floating gate.

David Schwaderer made a video of the presentation and posted it HERE.  Have a watch!

3D NAND: Benefits of Charge Traps over Floating Gates

Real California Cheese SealA prior post in this series (3D NAND: Making a Vertical String) discussed the difficulties of successfully manufacturing a charge trap flash bit.  Still, Spansion, and now other flash makers, have determined to take this route.  Why is that?

In Spansion’s case, a charge trap was a means of doubling the bit capacity of its products.  It was an inexpensive alternative to standard MLC flash.  To date this strategy has worked very well.

As mentioned in that earlier post, 3D NAND uses a charge trap because it’s extremely difficult to create features, like a floating gate, sideways – lithography works from the top down.  A charge trap, when used to replace a floating gate, doesn’t need to be patterned, since the Continue reading

3D NAND: How do You Access the Control Gates?

Samsung's TCAT NAND Flash Wordline COnnectionsOne of the thornier problems in making 3D NAND is the job of connecting the peripheral logic (the row decoders) to all of those control gates that are on layers buried somewhere within the bit array.  Remember that the control gates are the conductive sheets of polysilicon or tantalum nitride at various depths in the chip.

The problem boils down to this: You can’t run connections from each layer up or down the side of the chip to get to the CMOS circuits below.  Instead you have to create a terrace structure to expose and connect to each layer.

These connections are made by etching a stair-step pattern into the layers and sinking Continue reading

An Alternative Kind of Vertical 3D NAND String

Samsung's TCAT 3D NAND flashMy prior 3D NAND post explained how Toshiba’s BiCS cell works, using a silicon nitride charge trap to substitute for a floating gate.  This post will look at an alternative technology used by Samsung and Hynix which is illustrated in the first graphic, a diagram Samsung presented at a technical conference. This cell also uses a charge trap.

Let The Memory Guy warn you, if the process in my prior post seemed tricky, this one promises to put that one to shame!

Part of this stems from the use of a different kind of NAND bit cell.  You can shrink flash cells smaller if you use a high-k gate dielectric (one with a high dielectric constant “k”) since it Continue reading

SIA: Memories Drive Record Semi Revenues

SIA LogoThe SIA yesterday released the WSTS semiconductor sales data for September.  Monthly revenues reached a record $27 billion driving third-quarter revenues to their own record of $81 billion.  This was the seventh straight month of semiconductor growth, the first such run-up since 2010.

This quote, by SIA CEO Brian Toohey really caught The Memory Guy’s eye: “Sales of memory products have increased sharply compared to last year and continue to be a major driver of industry growth.”

A lot has been happening to drive this increase in memory revenues: The recent SK hynix fire increased DRAM prices, but Continue reading

3D NAND: Making a Vertical String

Toshiba's Original BiCS Diagram - IEDM 2007Let’s look at how one form of 3D NAND is manufactured.  For this post we will explore the original design suggested by Toshiba at the IEEE’s International Electron Device Meeting (IEDM) in 2007.  It’s shown in the first graphic of this post.  (Click on any of the graphics for a better view.)

Toshiba calls this technology “BiCS” for “Bit Cost Scaling.”  The technique doesn’t scale the process the way the world of semiconductors has always done to date – it scales the cost without shrinking the length and width of the memory cell.  It accomplishes this by going vertically, as is shown in this post’s first graphic.

This takes a special effort. This is where the real Continue reading

What is a 3D NAND?

Applied Materials' Explanation of 3D NANDIn the prior post we discussed the need to go vertically into the body of the die, since NAND flash can not be scaled much farther in length and width on the die’s surface.  Toshiba invented a 3D NAND which has been adopted and refined by all flash makers.  The idea is simple: Rather than shrink the cell’s length and width, why not turn the NAND string so that it’s standing on its end?

This concept is illustrated by this post’s first graphic, which was provided by Applied Materials.  (Click on the graphic to see the whole thing at a larger size.)  A standard NAND string that normally runs longitudinally is turned on its end to become a vertical string.  Not only that, but it makes things easier if the string is split into two sections and Continue reading

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Jim Handy Objective Analysis Memory Market Research +1 (408) 356-2549 Jim.Handy (at) Objective-Analysis.com

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