Why NAND is So Difficult to Scale
The graphic for this post (click to enlarge), supplied by ASML, the semiconductor industry’s leading lithography tool supplier, illustrates the challenge of migrating from one process node to the next. Across the bottom, on the X-axis, are representative process nodes ranging from “2D-45”, or two-dimensional (planar) 45nm NAND, to “3D-5x”, or three-dimensional 5xnm NAND. Below these numbers are the year of volume production.
The vertical axis, labeled “Tolerance” represents the minimum feature size of the chip, the minimum printable feature of a lithography tool, limits of lithography, and the tolerance of mask overlays.
The gray line in the middle represents the technology node as it is referred to by NAND manufacturers. You can see it progressing smoothly from 45nm to 35nm, then 25nm, then something below 20nm. On its way to 35nm this line crosses the upper dotted line which represents the 38nm resolution limit of a 1.35 NA (numerical aperture) immersion scanner based on a 193 nm ArF (Argon/Fluorine) excimer laser. If you can’t print features smaller than 38nm then how can NAND makers manufacture 35nm and smaller NAND flash chips? They use a technique called either “Spacer Assisted Double Patterning” or “Self-Aligned Double Patterning,” SADP, which will be detailed in an upcoming post. In brief, this approach allows features to be produced on the wafer at geometries half as wide as the scanner can print.
So you now have a way of producing features smaller than the smallest printable resolution on the wafer, but SADP has its limit too. Just below 20nm is another dotted line representing this limit. (It’;s actually just half of that same 38nm, or 19nm.) This would imply that today’s 19nm and 16nm processes might be impossible to manufacture. Fortunately a technique similar to double patterning can be used to produce quadruple patterning on the wafer, pushing NAND scaling well beyond 20nm.
It’s not hard to imagine that double patterning renders it more difficult to control exact features and tolerances, and quadruple patterning amplifies this challenge. These techniques are extraordinarily difficult to implement in a production environment.
When a manufacturer converts from standard lithography to a double-patterning approach the lithography tool resolution is relaxed, and this shows on the chart’s top blue line. This line shows the lithography requirements for each process. A 45nm process uses 45nm lithography. Since 35nm uses double-patterning, then the lithography backs off to 70nm, and the 25nm process uses 50nm lithography. At 16nm, since quadruple patterning is used, lithography backs off to 4 x 16nm = 64nm.
One big reason why NAND flash is so hard to scale is that, at every one or two process geometries, very significant process changes must be undertaken to keep shrinking the bits.
I haven’t addressed the last point in either curve. When NAND makers move to 3D NAND they expect to be able to take a big step backward in lithography and use scanners in the 55nm range without using double or quadruple patterning. The cost benefit of moving from 16nm to 3D stems from the fact that transistors are stacked on top of each other, an approach that allows the number of transistors per wafer to continue to scale with Moore’s Law even though process features grow rather than shrink. That is why Toshiba invented the term “Bit Cost Scaling” which underlies the “BiCS” name for its 3D NAND design. Bit costs continue to scale with Moore’s Law even though such scaling can no longer be achieved through lithography alone. This was explained in The Memory Guy’s series on 3D NAND.
The bottom line in the chart, “Overlay”, represents the mask overlap that can be tolerated from one mask to the next. You can see that this tolerance was also getting extremely tight. With the advent of 3D NAND the overlay tolerances will relax as well as the lithography requirements.
In summary, it has been challenging to migrate NAND flash to processes tighter than 45nm, and all kinds of exotic processes have been used to squeeze the technology down to 16nm, although lithography tools have not had to scale as aggressively as flash process technology. When 3D NAND is introduced, 55nm lithography equipment will be used since costs will be reduced by stacking transistors.