Gordon Moore’s Original 1965 Article

The Memory Guy recently received a question asking where to find Gordon Moore’s famous paper on Moore’s Law.  It seems that Moore’s seminal 1965 article is not very easy to find on the web.

I did a little digging myself and found a copy for ready download.  It’s still good reading.  The Computer History Museum gives access to the original 1965 article.  This page also features a follow-up article written ten years later in 1975, and a 1995 thirty-year review of the  phenomenon.

All are worth reading.

Back in 2010 I was able to attend the International Solid State Circuits Conference (ISSCC) in which Moore presented a keynote speech that looked back from an even more distant perspective.  A little digging found this presentation on The Engineering and Technology History Wiki in the form of a script and downloadable slides.  The presentation is titled “No Exponential is Forever“.  Although I know that Continue reading

Intel’s Optane DIMM Price Model

With Intel’s Cascade Lake rollout last month came with a co-introduction of 3D XPoint Memory in a DIMM form factor, the Optane DIMM that had been promised since the first introduction of 3D XPoint Memory in mid-2015.  A lot of benchmarks were provided to make the case for using Optane DIMMs (formally known as the Intel Optane DC Persistent Memory), but not much was said about the pricing, except for assertions that significant savings were possible when Optane was used to replace some of the DRAM in a large computing system.

So…  How much does it cost?  Well certain technical reports in resources like Anandtech probed sales channels to see what they could find, but The Memory Guy learned that the presentations Intel made to the press in advance of the Cascade Lake rollout contained not only prices for the three Optane DIMM densities (128, 256, & 512GB), but also provided the prices of the DRAM DIMMs that they were being compared against.  I’ll get to that in a moment, but first let’s wade through the fundamentals of Intel’s Optane pricing strategy to understand why Intel has needs to price it the way that it has.

In Objective Analysis’ report on 3D XPoint Memory, and in several presentations I have Continue reading

96-Layer NAND in Perspective: WDC Video

WDC 96-Layer NAND Model with The Memory GuyIt’s pretty easy to go from talking about the earliest 24-layer 3D NAND to talking about the next-generation 32-layer 3D NAND, and then to progress through 48, 64, and more layers, but the amazing scale of a 96-layer part doesn’t really sink in when you just talk about numbers.

That’s why The Memory Guy was so charmed when Western Digital Corp. (WDC) invited me in for a briefing that gave me a more solid idea of how significant of a number 96 really is.  The company brought along a plastic model that replicated the structure of its 96-layer BiCS NAND chip using clear plastic which was dramatically lighted from the inside.

WDC’s model was constructed using standard plastic sheeting, probably 1/8″ thick (~3mm), one sheet to represent the conductive polysilicon and one to represent the insulating silicon dioxide for each layer.  Naturally, there are more than 96 layers in 96-layer NAND since there are source select transistors at the bottom and drain select transistors at the top.  This adds a little bit to the layer count.

Another layer in the middle of Continue reading

What’s Inside an Optane DIMM?

Part of Optane DIMM LogoWith the release of its Cascade Lake family of processors today (formally called the “2nd Generation Intel Xeon Scalable processor”) Intel disclosed more details about its Optane DIMM, which has been officially named the “Intel Optane DC Persistent Memory.”  This DIMM’s architecture is surprisingly similar to an SSD, even to the point of its having error correction and encryption!

The Memory Guy doesn’t generally cover SSDs, but I do cover DIMMs, so this is one of those posts that I could have put into either of my blogs: The Memory Guy or The SSD Guy.  I have decided to put it here with the hopes that it will be easier for members of the memory community to find.

The internal error correction, the encryption, and the fact that 3D XPoint Memory wears out and must use wear leveling, all cause the Optane DIMM’s critical timing path to be slower than the critical path in a DRAM DIMM, rendering the Optane DIMM unsuitable for code execution.  This, and the fact that XPoint writes are slower than its reads, all help to explain why an Optane DIMM is never used as the only memory in a system: there is always a DRAM alongside the Optane DIMM to provide faster Continue reading

MRAMs to Power Cell Phones

Spin i Reversed Below the EquatorThe Memory Guy today became aware of a significant breakthrough in magnetic memory technologies (MRAM) that could prove to be a big bonus for mobile applications.  These memories could be used to generate power as well as to store data.

Scientists have only recently become aware of an oversight stemming from the fact that nearly all spin magnetics research has been performed in the northern hemisphere.  Just as the water in a drain rotates counterclockwise in the northern hemisphere but clockwise in the southern hemisphere, the Coriolis Effect dictates that magnetic spin has the opposite sense above the equator as below.

This surprise finding was made when researchers from Stüdpfalz University of Blindman’s Bluff, Iowa, brought samples of an STT MRAM they had developed to the Townsville City Metropolitan University in Queensland, Australia, where researchers have been producing similar magnetic memories below the equator.  Until that moment neither team had thought to question the Continue reading

Video: What’s Driving Tomorrow’s Semiconductors?

Samsung ForumIn early February the Samsung Strategy & Innovation Center asked for The Memory Guy to present an outlook for semiconductors as a part of the company’s Samsung Forum series.

Samsung kindly posted a video of this presentation on-line for anyone to watch.

Naturally, the presentation is memory-focused since it consists of the Memory Guy presenting to the world’s leading memory chip supplier.  Still, it also covers total semiconductor revenues and demand drivers for future non-memory technologies, as well as memory chips.

During the presentation I explained that the next few years will bring semiconductors into new applications while chips will maintain their strength in existing markets. I showed how semiconductor demand doesn’t change much over time, but that the real swing factor in chip revenues is Continue reading

Forecast Videos Prove A History of Accuracy

ForecastsEvery year the folks at VLSI Research provide The Memory Guy with an opportunity to share the latest Objective Analysis forecast with the world.  They record a 20-minute video highlighting the forecast in a conversation between me and VLSI’s chairman, Dan Hutcheson.

There are now twelve videos on the site, one for each year from 2008 to 2019.  That’s quite a collection!

Over the course of each video I not only present the forecast, but also give an overview of the thinking behind it.  Typically I explain the impact of high or low capital spending in prior years, but in some forecasts I explain how other issues (in particular NAND flash’s excruciating conversion from planar to 3D) can create a shortage independent of capital spending patterns.

We also go over what went right or wrong with the prior year’s forecast.  Things that  go wrong are generally macroeconomic issues like the Continue reading

NV Stacked Memory: Selectors and Forming (Part 1)

Ron NealeContributor Ron Neale analyzes selector technologies presented by CEA Leti at the 2018 IEDM conference last December.

At the close of last year the IEDM maintained its long-standing reputation for offering across-the-board the right focus at the right time on important and key parts of the electronic device discipline.   For those with an interest in the future of stacked or 3D NV-memory arrays there were a number of important papers and presentations on a variety of thin film memory selectors or matrix isolation devices (MIDs).

Important, because as the move towards stacked memory arrays for storage class memory (SCM) and persistent  memory (PM) applications gains momentum, the thin film selector may be the device which is key in determining the performance and reliability for a number of different types of NV memory arrays or even the very existence of that type of memory array.  One of the important and poorly understood variables in the mix is the selector forming voltage and the structural changes which lead from it to the operating device threshold voltage which, in my view needs a lot more by way of detailed understanding.

As the memory array moves into Continue reading

Memory Sightings at ISSCC

ISSCC LogoThis week the International Solid State Circuits Conference (ISSCC) was held in San Francisco.  What was there?  The Memory Guy will tell you!

NAND Flash

There were three NAND flash papers, one each from Toshiba, Samsung, and Western Digital Corp. (WDC).

Toshiba 96-layer 1Tb QLC NANDToshiba described a 96-layer QLC 1.33 terabit chip.  Like the chip that Toshiba presented last year, this one uses CUA, which Toshiba calls “Circuit Under Array” although Micron, who originated the technology, says that CUA stands for “CMOS Under Array.”  Toshiba improved the margins between the cells by extending the gate threshold ranges below zero, a move that forced them to re-think the sense amplifiers.  They also implemented a newer, faster, lower-error way to Continue reading

Emerging Memories Today: Forecasting Emerging Memories

Emerging Memory ParadeReaders who have been following this series will note that The Memory Guy has so far described everything pertaining to emerging memory technologies except for the market outlook.  In this post I will share some key elements of our emerging memory forecast.

Since this is a simple blog post the forecast coverage is brief.  The detailed forecast appears in the report that is the basis of this blog post series: Emerging Memories Poised to Explode.

The first large-scale applications poised to replace today’s standard NOR flash with a new memory technology will be the embedded memories in CMOS logic chips that are processed on advanced process nodes (processes of 28nm and smaller.)  Many CMOS logic chips use NOR flash, especially microcontrollers (MCUs) which are found in a very broad range of applications.  The vast majority of MCUs, though, are uncomplicated and can therefore be economically produced on larger, older process nodes like 90nm and greater.

At tighter processes flashless versions of some MCUs already ship that can Continue reading