Although Objective Analysis has published its “Brief” format white papers for some time, this line has never received the focus that it deserves. To remedy that, we are taking the most interesting and timeless of the Insights that we have published on membership website Smartkarma and providing them to our friends for a reasonable price.
The Brief is a very short report format used to make a succinct Continue reading “Introducing New Objective Analysis Briefs”
During his December 15 IEDM keynote speech, Samsung Electronics Chairman Kinam Kim really surprised me. He spoke favorably of the approach that YMTC is using to produce 3D NAND flash.
This approach, which YMTC named “Xtacking,” involves the use of two separate wafers to manufacture a 3D NAND chip. The brief way to describe it is to say that Continue reading “Did Samsung Just Endorse YMTC’s Xtacking?”
Objective Analysis and Coughlin Associates are hosting a free webinar on November 30 to help SEMICON West attendees get the most out of their show visit.
How can you really benefit from your your show attendance? What kinds of questions will you be asking to make sure that your emerging memories strategy is on point? What companies Continue reading “Free Interactive Webinar: Your New Memory Strategy for SEMICON West”
If you ask any two people in the computing industry to define the term “Storage Class Memory” you’re likely to get three or more answers. That’s because the term isn’t well defined anywhere.
Some people use it for emerging memory technologies like MRAM, ReRAM, FRAM, and PCM/XPoint. Others include NAND flash, even in the form of Continue reading “What Exactly IS “Storage Class Memory”?”
This post shares a new and entertaining animation by Charlotte Streeter that offers one interpretation of the inner workings of one type of SiO-based nonvolatile memory like those described in Ron Neale’s most recent post on The Memory Guy.
The video links the observed electrical characteristics to the structural Continue reading “Video: The Inner Workings of SiO ReRAM”
Intel has recently announced a technology that the company calls PowerVia that could inadvertently help reduce the cost of HBM – high-bandwidth memory.
HBM is a stack of up to twelve DRAM chips that are interconnected using over one thousand TSVs – Through-Silicon Vias. These are metal-filled holes etched right through the DRAM die to allow signals to move vertically through the chip. It’s an alternative to more conventional wire bonding.
HBM sells for significantly more than Continue reading “Could Intel’s PowerVia Lower HBM Costs?”
In this post contributor Ron Neale analyzes Weebit Nano’s recently-announced memory array, based on SiO and an Ovonic Threshold Switch selector developed by CEA-Leti in France. Ron employs his extensive background in Ovonic devices to try and sleuth out the characteristics of both the memory element and the selector, and to understand some of the inner workings of the cell.
Weebit-Nano (Hod Hasharon, Israel), have recently reported some first steps on the path they have outlined to meet their bold claim of Continue reading “Weebit-Nano’s First Small Steps on the NV Memory Road”
The Memory Guy is pleased to announced the release of a new report by Objective Analysis and Coughlin Associates: Emerging Memories Take Off.
The report is the 2021 update of our popular 2020 emerging memories report, and includes detailed technology profiles of MRAM, ReRAM, FRAM, PCM/XPoint and other technologies, profiles of Continue reading “New Report: Emerging Memories Take Off”
From time to time The Memory Guy is asked to explain why the NAND flash business doesn’t immediately convert to the next larger number of bits per cell once it becomes available. Many people tend to think that a significant cost benefit will necessarily result from migrating to the next number of bits. It surprises these folks to find that the cost advantage of moving from TLC to QLC is only half as great as the benefit of moving from SLC to MLC.
There is a diminishing Continue reading “SLC to MLC to TLC to QLC to PLC: Diminishing Returns”
Ron Neale enjoyed an extensive e-mail correspondence with Professor Carlos Paz de Araujo of the University of Colorado in Colorado Springs, and founder of Symetrix, about Symetrix’ new approach to ferroelectric memory technology. In this post Ron provides an overview of that conversation that provides significant insight into why FRAMs hit their limit at 180nm, and why they suddenly have opportunities at the most advanced process lithographies.
Ferroelectric memory was one of the earliest and first of the non-volatile (NV) emerging memory technologies to make significant Continue reading “Symetrix: The Next Big Step for FeFETs”