Hprobe: a test equipment manufacturer based in Grenoble France, has cast its vote for MRAM to succeed in the emerging memory battle. It has created a piece of production test equipment dedicated to MRAM technology.
The company has developed a new perpendicular magnetic generator module that allows Continue reading “Hprobe’s Vote for MRAM”
Almost one year ago Tom Coughlin and The Memory Guy presented the findings of our first emerging memories report at the Storage Networking Industry Association’s (SNIA) Storage Developers Conference (SDC). The podcast of this presentation has just been made available on the SNIA website.
In the podcast, titled “The Long and Winding Road to Persistent Memories,” Tom and I reviewed leading emerging memory technologies as we had surveyed them for our report.
This is a highly visual presentation, so I would recommend following along with the slides, which can also be downloaded from the SNIA SDC website at HERE. That same page combines the slides and the podcast into a video, so if you’re able to, it might be a good idea to watch the video. If you’re driving as your listening to it, though, then please use the podcast instead!
In the time since that podcast was recorded Tom and I have updated the report to a 2019 edition, which can be Continue reading “Podcast: Storage Developer Conference 2018 – Emerging Memories”
In this third part of a four-part series, contributor Ron Neale continues his analysis of selector technologies focusing the nature of the mystery of Forming and a number of the many unanswered questions.
From Part 2 of this series it is very clear that only a detailed and accurate description of threshold switching will allow an assessment of what might be possible during the act of Forming, when the threshold voltage of a selector or memory (if the latter is fabricated in its amorphous state) is reduced in some cases by a factor more than 30% from its as-fabricated value. The problem is that there have been numerous attempts to account for the threshold switching mechanism. In Part 3 of this series I will briefly explore some of threshold switching options and search for any which might be used to account for Forming.
Threshold switching: The key.
If understanding what is happening during threshold switching is the key to what might be possible during that single cycle of threshold switching associated with selector Forming, then there is a possible converse connotation: If we really understand what is happening Continue reading “NV Memory Selectors: Forming the Known Unknowns (Part 3)”
This week’s HotChips conference featured a concept called “Processing in Memory” (PIM) that has been around for a long time but that hasn’t yet found its way into mainstream computing. One presenter said that his firm, a French company called UPMEM, hopes to change that.
What is PIM all about? It’s an approach to improving processing speed by taking advantage of the extraordinary amount of bandwidth available within any memory chip.
The arrays inside a memory chip are pretty square: A word line selects a large number of bits (tens or hundreds of thousands) which all become active at once, each on its own bit line. Then these myriad bits slowly take turns getting onto the I/O pins.
High-Bandwidth Memory (HBM) and the Hybrid Memory Cube (HMC) try to get past this bottleneck by stacking special DRAM chips and running Continue reading “UPMEM Processor-in-Memory at HotChips Conference”
Contributor Ron Neale continues his analysis of selector technologies focusing the nature of the mystery of Forming and a number of the many unanswered questions.
Thin film selectors, or memory matrix isolation devices, based on chalcogenide glasses, would appear to be the devices of choice as non-volatile memory arrays move towards 3D stacked structures. Considerable progress has been made in finding selector compositions which can be doped to provide a suitable level of structural stability required for the NV memory array application. These were discussed in the first part of this series.
However, there is one known unknown in relation to this type of selector and it is the need for Forming, with the unknown being the physical nature of the changes which occur within the device as a result of the Forming process and any implications those changes might have on reliability and performance. The outward manifestation of Forming is a change in threshold voltage from an initial value to some lower more constant operating value. Not just a minor threshold voltage change but a significant one, a reduction of the order 36% in some cases.
The diagram below illustrates Continue reading “NV Stacked Memory Selectors: Forming the Known Unknowns (Part 2)”
Readers have asked when I will be speaking at the Flash Memory Summit. There will be a number of opportunities to see me there.
Before I give details, I should make sure that anyone who is unfamiliar with the show knows that this is an annual event that has grown steadily over the past 14 years to become the biggest show of its kind. It is held in the Santa Clara Convention Center in Santa Clara, California, in early August. This year it will be Tuesday-Thursday, August 6-8, and is preceded by the MRAM Developer Day.
Here are the details of Continue reading “My Flash Memory Summit Schedule”
Tom Coughlin and I are proud to announce that we have released an update of our popular emerging memory report. This report, titled Emerging Memories Ramp Up, covers all leading emerging memory technologies from PCM and 3D XPoint through MRAM and ReRAM to less-known types like carbon nanotubes and polymeric FRAMs.
Anyone who makes or uses memory chips, or who is involved in this ecosystem as an investor or tool supplier needs to read and understand this study to prepare for one of the biggest changes in the history of the chip market. The report’s wealth of information will allow companies to make strategic plans to gain a competitive edge.
The report’s forecast model has determined that the emerging memory market will grow to $20 billion by 2029 largely by displacing today’s less efficient Continue reading “Emerging Memory Report Updated”
The Memory Guy will be speaking at SEMICON West. Perhaps I will meet one or more readers there.
My presentation is Monday, July 8, at 3:55-4:25 in the 2019 SEMI Market Symposium. I will be one of eight speakers who will provide our outlooks of the chip market. All of my co-presenters are well known in their fields and will doubtlessly provide valuable insights on what tomorrow has to offer.
My presentation will be a rapid-fire onslaught of valuable information proving that certain outcomes are nearly inevitable and showing how they should evolve over time.
I will specifically discuss today’s down-cycle, the end of More’s Law, semiconductor process changes, including materials and production technologies, changes in end-use architectures (and the impact they will have), the imporatance of new end markets like 5G, and geographical and political issues, especially those dealing with today’s US/China trade war.
The semiconductor industry is in the early stages of Continue reading “SEMICON West: See Me There”
The Memory Guy recently received a question asking where to find Gordon Moore’s famous paper on Moore’s Law. It seems that Moore’s seminal 1965 article is not very easy to find on the web.
I did a little digging myself and found a copy for ready download. It’s still good reading. The Computer History Museum gives access to the original 1965 article. This page also features a follow-up article written ten years later in 1975, and a 1995 thirty-year review of the phenomenon.
All are worth reading.
Back in 2010 I was able to attend the International Solid State Circuits Conference (ISSCC) in which Moore presented a keynote speech that looked back from an even more distant perspective. A little digging found this presentation on The Engineering and Technology History Wiki in the form of a script and downloadable slides. The presentation is titled “No Exponential is Forever“. Although I know that Continue reading “Gordon Moore’s Original 1965 Article”
With Intel’s Cascade Lake rollout last month came with a co-introduction of 3D XPoint Memory in a DIMM form factor, the Optane DIMM that had been promised since the first introduction of 3D XPoint Memory in mid-2015. A lot of benchmarks were provided to make the case for using Optane DIMMs (formally known as the Intel Optane DC Persistent Memory), but not much was said about the pricing, except for assertions that significant savings were possible when Optane was used to replace some of the DRAM in a large computing system.
So… How much does it cost? Well certain technical reports in resources like Anandtech probed sales channels to see what they could find, but The Memory Guy learned that the presentations Intel made to the press in advance of the Cascade Lake rollout contained not only prices for the three Optane DIMM densities (128, 256, & 512GB), but also provided the prices of the DRAM DIMMs that they were being compared against. I’ll get to that in a moment, but first let’s wade through the fundamentals of Intel’s Optane pricing strategy to understand why Intel has needs to price it the way that it has.
In Objective Analysis’ report on 3D XPoint Memory, and in several presentations I have Continue reading “Intel’s Optane DIMM Price Model”