Video: The Inner Workings of SiO ReRAM

A cartoon of the atoms in a memory cell for an oxygen vacancy resistive RAMThis post shares a new and entertaining animation by Charlotte Streeter that offers one interpretation of the inner workings of one type of SiO-based nonvolatile memory like those described in Ron Neale’s most recent post on The Memory Guy.

The video links the observed electrical characteristics to the structural Continue reading “Video: The Inner Workings of SiO ReRAM”

Could Intel’s PowerVia Lower HBM Costs?

Photo of NVIDIA Ampere GPU with six HBM stacks at top & bottomIntel has recently announced a technology that the company calls PowerVia that could inadvertently help reduce the cost of HBM – high-bandwidth memory.

HBM is a stack of up to twelve DRAM chips that are interconnected using over one thousand TSVs – Through-Silicon Vias.  These are metal-filled holes etched right through the DRAM die to allow signals to move vertically through the chip.  It’s an alternative to more conventional wire bonding.

HBM sells for significantly more than Continue reading “Could Intel’s PowerVia Lower HBM Costs?”

Weebit-Nano’s First Small Steps on the NV Memory Road

Photo of Ron Neale, Renowned Phase-Change Memory ExpertIn this post contributor Ron Neale analyzes Weebit Nano’s recently-announced memory array, based on SiO and an Ovonic Threshold Switch selector developed by CEA-Leti in France.   Ron employs his extensive background in Ovonic devices to try and sleuth out the characteristics of both the memory element and the selector, and to understand some of the inner workings of the cell.


Weebit-Nano (Hod Hasharon, Israel), have recently reported some first steps on the path they have outlined to meet their bold claim of Continue reading “Weebit-Nano’s First Small Steps on the NV Memory Road”

New Report: Emerging Memories Take Off

Fighter Jets Doing Acrobatic Take-OffThe Memory Guy is pleased to announced the release of a new report by Objective Analysis and Coughlin Associates: Emerging Memories Take Off.

The report is the 2021 update of our popular 2020 emerging memories report, and includes detailed technology profiles of MRAM, ReRAM, FRAM, PCM/XPoint and other technologies, profiles of Continue reading “New Report: Emerging Memories Take Off”

SLC to MLC to TLC to QLC to PLC: Diminishing Returns

Chart shows asymptotically diminishing cost reductions achieved by migrating from SLC to MLC to TLC to QLC to PLCFrom time to time The Memory Guy is asked to explain why the NAND flash business doesn’t immediately convert to the next larger number of bits per cell once it becomes available.  Many people tend to think that a significant cost benefit will necessarily result from migrating to the next number of bits.  It surprises these folks to find that the cost advantage of moving from TLC to QLC is only half as great as the benefit of moving from SLC to MLC.

There is a diminishing Continue reading “SLC to MLC to TLC to QLC to PLC: Diminishing Returns”

Symetrix: The Next Big Step for FeFETs

Photo of Ron Neale, Renowned Phase-Change Memory ExpertRon Neale enjoyed an extensive e-mail correspondence with Professor Carlos Paz de Araujo of the University of Colorado in Colorado Springs, and founder of Symetrix, about Symetrix’ new approach to ferroelectric memory technology.  In this post Ron provides an overview of that conversation that provides significant insight into why FRAMs hit their limit at 180nm, and why they suddenly have opportunities at the most advanced process lithographies.


Ferroelectric memory was one of the earliest and first of the non-volatile (NV) emerging memory technologies to make significant Continue reading “Symetrix: The Next Big Step for FeFETs”

White Paper: The Future of Low-Latency Memory

Chart showing areas in the capacity-bandwidth space where DDR4, DDR5, HBM2E and OMI fitTom Coughlin and I have just published a new white paper that is now available on the Objective Analysis website.  It examines the way that  processors communicate with DRAM, and how problems that stem from loading get in the way of increasing speed.

We compare DDR against HBM (High Bandwidth Memory) and a newer Continue reading “White Paper: The Future of Low-Latency Memory”

Putting the Brakes on Added Memory Layers

Close-up of a part of the blog post's main graphicFor some time two sides of the computing community have been at odds.  One side aims to add layers to the memory/storage hierarchy while other side is trying to halt this growth.

This has been embodied by recent attempts to stop using objective nomenclature for cache layers (L1, L2, L3) and moving to more subjective names that aim to limit any attempt to add another new layer.

This is a matter close to my heart, since Continue reading “Putting the Brakes on Added Memory Layers”

Micron Bows Out of 3D XPoint Business

Photo of Micron's Lehi, Utah, wafer fabrication plantIn an investor conference call today Micron Technology announced that it would discontinue further development of the 3D XPoint memory that the company had developed in partnership with Intel, phasing out production and selling off the Lehi, Utah fab (pictured) that makes 3D XPoint.

Micron said that it has determined that the market for the product is too small to Continue reading “Micron Bows Out of 3D XPoint Business”

ZnTe Selectors to Solve NVM Fabrication Problems

Photo of Ron Neale, Renowned Phase-Change Memory ExpertContributor Ron Neale joins us again to review a recently-published article in the journal Nature Scientific Reports.   While the main focus of the paper is on using a nitrogen environment to generate stable memory selectors from ZnTe, it also provides some new inputs through which he finds further support of his theories of Forming and device behavior.


A recently-published Nature Scientific Reports article by a research team from Hanyang and Kunsan Universities in The Republic of Korea focuses on Continue reading “ZnTe Selectors to Solve NVM Fabrication Problems”