Month: April 2013

Hybrid Memory Cube Making Progress

Conceptual Cutaway Drawing of the Hybrid Memory CubeOn Tuesday the HMC Consortium (that’s short for “Hybrid Memory Cube”) announced that members have agreed upon a specification.  The consortium has been moving rapidly, meeting its targets despite the revolutionary nature of the interface.

As a reminder, this technology stacks multiple DRAMs in a single package with a logic chip at the base of the stack that performs all the signalling to the rest of the system.  Signals between the DRAMs and logic chip use through-silicon vias (TSVs) as interconnections.  This allows the technology to deliver 15 times the performance of DDR3 at only 30% of the power consumption.  The Memory Guy first posted about the HMC in late 2011.

The consortium explains that the HMC interface already has 100 adopters, and that a few Continue reading “Hybrid Memory Cube Making Progress”

New Memory Bonding Technique Shows Promise

Spider Attaching Bonding Wires on Multi-Chip StacksIn a new cross-disciplinary effort, researchers have developed a novel approach to attach bonding wires to stacks of memory chips.  The new technique, being called a “breakthrough” by its developers, promises to allow chips to be stacked to several times their current 8-chip and 16-chip heights.

At issue is the challenge of precisely bonding wires a fraction of the diameter of a human hair over great distances without their inadvertently coming into contact with their neighbors to create a short circuit.  Such a short could destroy one or more of the chips in the stack, rendering the entire stack useless.  The mechanical means of attaching these wires, although highly sophisticated, still has significant issues, that limit the economics of higher stacks.

Researchers at the Berea University of Geology (BUG) in Berea, Kentucky, noticed that certain Continue reading “New Memory Bonding Technique Shows Promise”