With all the new emerging memories that are being developed there must be quite a number of test runs to study exactly how well these new technologies and materials can perform. If a batch of 300mm wafers must be used for a single test then the cost multiplies, particularly if no other test can be run on that wafer.
Another great difficulty is that most memory manufacturers run their wafers on very high-efficiency and high-volume wafer fabs. It is perilous and wasteful to interrupt a production process to inject a batch of test wafers. Most fab managers would rather have a tooth pulled than to change their flow to accept an experimental lot.
What can be done to improve this situation?
Well the folks at Intermolecular, Inc. (IMI) explained to the Memory Guy that they have a solution: They have built a small fab that allows single wafers to be processed with varying parameters across a single wafer. In this way one wafer can be used to run 36 or more different experiments all at the same time. This is clearly more economical than having to run the experiment on 36 wafers or, even worse, 36 batches of wafers! Intermolecular says that, while production fabs are optimized for manufacturing, their fab is optimized for materials understanding.
The firm calls itself an Continue reading “Accelerating New Memory Materials Research”
The previous post in this series (excerpted from the Objective Analysis and Coughlin Associates Emerging Memory report) explained why emerging memories are necessary. Oddly enough, this series will explain bit selectors before defining all of the emerging memory technologies themselves. The reason why is that the bit selector determines how small a bit cell can get, and that is a very significant component of the overall cost of the technology. Cost, of course, is extraordinarily important because no system designer would use a component that would make a system more expensive than it absolutely needs to be!
A number of the Memory Guy’s readers may never have heard of a selector. I’ll explain it here. It’s not complicated.
Every bit cell in a memory chip requires a selector. This device routes the bit cell’s contents onto a bus that eventually makes its way to the chip’s pins, allowing it to be read or written. The bit cell’s technology determines the type of selector that is appropriate: SRAMs use two transistors, DRAMs use one transistor, and flash memories combine a transistor with the Continue reading “Emerging Memories Today: Understanding Bit Selectors”
What really happens in NAND flash during an MLC, TLC, or QLC write? Although there are lots of websites that explain that multilevel cells store four, or eight, or sixteen different voltage levels on a cell (for MLC, TLC, or QLC), they don’t spell out the process of putting those voltage levels onto the bit cell.
Fortunately, Vic Ye, Manager, NAND Flash Characterization at Yeestor Microelectronics Co., Ltd. in Shenzhen, China presented the programming process in a series of short videos at the Flash Memory Summit last August. The Memory Guy was fortunate enough to attend his presentation. Yeestor is a fabless semiconductor manufacturer that manufactures flash storage controllers for SSDs (PCIe & SATA) and flash cards (SD, UFS, eMMC, etc.)
Mr. Ye later gave me permission to share his videos and these are the foundation of this post. They’re brief (13 seconds to 1:10) so they won’t take much time to review. The videos were a part of his slide presentation titled: A Graphical Journey into 3D NAND Program Operations that can be downloaded from The Flash Memory Summit website by clicking the presentation title above and entering your e-mail address.
A multilevel flash bit cell has Continue reading “Videos Demystify MLC NAND Programming”
Non-silicon memory technologies have been studied for about as long as have silicon-based technologies, but the silicon technologies have always been preferred. Why is that, and why should anything change?
This is a question that The Memory Guy is often asked. The answer is relatively simple.
Silicon memory technologies benefit from the fact that they have always been manufactured on process technologies that are nearly identical to those used to produce CMOS logic, and can therefore take advantage of the advancements that are jointly developed for both memory and logic processes. In fact, before the middle 1980s, logic and memory processes were identical. It wasn’t until then that the memory market grew large enough (over $5 billion/year) that it could support any additional process development on its own.
Even so, memory processes and logic processes are more similar than different. This synergy between memory and logic continues to reduce the process development cost for both memories and logic.
Emerging memories depart from Continue reading “Emerging Memories Today: Why Emerging Memories are Necessary”
Ever since moving to Silicon Valley some time ago The Memory Guy has worked with a number of impressively-talented engineers from India. Some are educated in the US, while others are educated in India. One university that produces excellent engineers is the Indian Institute of Technology, or IIT.
It comes as no surprise, then, to find a valuable resource produced by an IIT faculty member. Dr. Sparsh Mittal, an assistant professor at IIT Hyderabad, reached out to me to share some papers that he thought might be of interest to Memory Guy readers. They were a few of roughly 40 papers that he has posted on his publications page. He explained that he previously worked at Oak Ridge National Lab, in the US.
Dr. Sparsh has published several very comprehensive surveys on memory systems, both conventional and emerging, covering topics like DRAM reliability, NVM/Flash, ReRAM-based processing-in-memory, and the architecture of neural networks. The web page lists 34 surveys, eight of them Continue reading “Valuable Memory Technical Resources”
There’s never been a more exciting time for emerging memory technologies. New memory types like PCM, MRAM, ReRAM, FRAM, and others have been waiting patiently, sometimes for decades, for an opportunity to make a sizeable markets of their own. Today it appears that their opportunity is very near.
Some of these memory types are already being manufactured in volume, and the established niches that these chips sell into can provide good revenue. But the market is poised to experience a very dramatic upturn as advanced logic processing nodes drive sophisticated processors and ASICs to adopt emerging persistent memory technologies. Meanwhile Intel has started to aggressively promote its new 3D XPoint memory for use as a persistent (nonvolatile) memory layer for advanced computing. It’s no wonder that SNIA, JEDEC, and other standards bodies, along with the Linux community and major software firms are working hard to implement the necessary standards and ecosystems to support widespread adoption of the persistent nature of these new technologies.
This post introduces a Continue reading “Emerging Memories Today: New Blog Series”
It’s earnings call season, and we have heard of a slowing DRAM market and NAND flash price declines from Micron, SK hynix, Intel, and now Samsung. DRAM prices have stopped increasing, and that can be viewed as a precursor to a price decline.
Samsung’s 31 October, 2018 3Q18 earnings call vindicated Objective Analysis‘ forecast for a 2H18 downturn in memories that will take the rest of the semiconductor market with it.
Those familiar with our forecast know that for a few years we have been predicting a downturn in the second half of this year as NAND flash prices fall, followed by a DRAM price collapse. After the DRAM collapse the rest of the semiconductor market will undergo a downturn.
We’ve been calling for this downturn for some time. Dan Hutcheson at VLSI Research has been videotaping our forecast every December for the past Continue reading “Memory Market Falling, as Predicted”