Month: April 2021

Symetrix: The Next Big Step for FeFETs

Photo of Ron Neale, Renowned Phase-Change Memory ExpertRon Neale enjoyed an extensive e-mail correspondence with Professor Carlos Paz de Araujo of the University of Colorado in Colorado Springs, and founder of Symetrix, about Symetrix’ new approach to ferroelectric memory technology.  In this post Ron provides an overview of that conversation that provides significant insight into why FRAMs hit their limit at 180nm, and why they suddenly have opportunities at the most advanced process lithographies.

Ferroelectric memory was one of the earliest and first of the non-volatile (NV) emerging memory technologies to make significant Continue reading “Symetrix: The Next Big Step for FeFETs”

White Paper: The Future of Low-Latency Memory

Chart showing areas in the capacity-bandwidth space where DDR4, DDR5, HBM2E and OMI fitTom Coughlin and I have just published a new white paper that is now available on the Objective Analysis website.  It examines the way that  processors communicate with DRAM, and how problems that stem from loading get in the way of increasing speed.

We compare DDR against HBM (High Bandwidth Memory) and a newer Continue reading “White Paper: The Future of Low-Latency Memory”

Putting the Brakes on Added Memory Layers

Close-up of a part of the blog post's main graphicFor some time two sides of the computing community have been at odds.  One side aims to add layers to the memory/storage hierarchy while other side is trying to halt this growth.

This has been embodied by recent attempts to stop using objective nomenclature for cache layers (L1, L2, L3) and moving to more subjective names that aim to limit any attempt to add another new layer.

This is a matter close to my heart, since Continue reading “Putting the Brakes on Added Memory Layers”