Let’s look at how one form of 3D NAND is manufactured. For this post we will explore the original design suggested by Toshiba at the IEEE’s International Electron Device Meeting (IEDM) in 2007. It’s shown in the first graphic of this post. (Click on any of the graphics for a better view.)
Toshiba calls this technology “BiCS” for “Bit Cost Scaling.” The technique doesn’t scale the process the way the world of semiconductors has always done to date – it scales the cost without shrinking the length and width of the memory cell. It accomplishes this by going vertically, as is shown in this post’s first graphic.
This takes a special effort. This is where the real genius comes in.
In planar NAND horizontal strips of polysilicon are used for the wordlines that connect the control gates of the memory cells (the lines labeled WL0 through WL31 in the second graphic). In 3D NAND these are replaced with horizontal sheets of polysilicon.
How are these sheets manufactured? First a layer of CMOS logic is built on the chip to serve as the peripheral logic and conductive paths are produced on the substrate to connect pairs of adjacent columns to form the “U” shaped cell shown as the first graphic in the prior post: “What is a 3D NAND?” This logic is then insulated with a layer of silicon dioxide. A conductive polysilicon layer is deposited on top of this to form the first wordline and control gate, and a silicon dioxide layer is grown on top of the polysilicon to insulate it from the polysilicon layer that will be deposited above it. This is repeated a number of times with pairs of polysilicon and silicon dioxide layers laid one above another as sheets across the entire wafer. It’s something like a layer cake with alternating layers of cake and frosting. This is shown as “a” in the third graphic.
Once the desired number of these layers has been deposited upon the wafer, an array of circular holes is patterned onto it and these holes are then etched through all of the layers to the substrate. A single hole is shown in “b” in the figure. This type of etching is a technique borrowed from the DRAM trench cell that was used by IBM, Toshiba, Siemens, and their licensees.
Only a single mask step is needed to form the holes for all the layers in the device. Even though the string may have 16, 32, 64, or more transistors, it’s still just a single mask step. This creates very economical lithography compared to today’s NAND fabrication processes.
Next comes the fun of making the floating gate and the channel. The inside walls of the holes are first coated with a silicon dioxide layer (“c” in the graphic) to create the gate dielectric (the dielectric between the control gate and the floating gate). Think of this as a tube lining the hole. Then the floating gate is made by depositing a silicon nitride layer onto the silicon dioxide, forming a tube within the tube – “d” in the graphic. Another oxide layer is deposited on the silicon nitride to form the tunnel dielectric (“e” in the graphic) – the third of three concentric tubes lining the walls of the hole. Finally the entire hole (or what’s left of it after these concentric tubes have been layered on the sidewalls) is filled by depositing polysilicon into it (“f” in the graphic). In the end this produces a NAND string that behaves similar to the one in the second graphic.
After the holes are processed another lithography/etch cycle is used to carve long slits for the length of the array between the adjacent connected columns to isolate the control gates of the “Up” column from those of the “Down” column.
From a lithographic viewpoint, the width of the NAND flash string is limited by the thickness of the walls of the tubes lining the hole, and the thickness of the polysilicon channel. Once these features have reached a certain thickness they will no longer be able to shrink any further, limiting the number of columns that can be packed into an area of a chip. Today we don’t know where that limit is. We also don’t know the maximum number of layers this technology can achieve. In other words, 3D NAND could stay around much longer than the 3 generations that are currently projected.
What is most interesting is the fact that lithography will actually move backwards at the onset of 3D and will probably progress very slowly (if at all) as 3D advances to future chip densities. This is why Toshiba coined the term: “Bit Cost Scaling”. The objective of 3D is to continue to reduce costs to follow Moore’s Law without using lithographic shrinks. This is a completely different approach than has ever been tried in semiconductors.
Astute readers will note that I didn’t say anything about patterning the floating gate. That’s because it’s very difficult to pattern anything vertically – you can’t do it using lithography since you can’t make the light go sideways. This is where some real magic comes into play.
The original BiCS design uses a silicon nitride charge trap as a substitute for the floating gate – the same technique that Spansion has used since the 2002 introduction of its MirrorBit NOR flash. This technology is highly manufacturable and now accounts for roughly 80% of Spansion’s NOR flash production. A charge trap is an insulating layer, so two adjacent charge traps will not interfere with each other even though there is no distinction between each cell’s charge trap. This layer doesn’t need to be patterned at all.
Charge traps will be used for all 3D NAND for this reason.
The big problem here is that nobody but Spansion has successfully produced charge trap flash in volume. Before it was acquired by Spansion in 2008 a company named Saifun licensed charge trap technology to a number of firms, including Macronix, NEC, Qimonda, SMIC, Sony, and Tower, but none of these licensees were able to move beyond prototypes and into production. Samsung announced a charge trap flash for its 40nm node in 2006, but never released the part to production. Objective Analysis anticipates that the cause of these difficulties, whatever it may be, could delay the introduction of 3D NAND.
SanDisk presented a very clear illustration of a BiCS vertical structure in its May 2014 Investor Day presentations, and has allowed me to include a copy of it here. The company didn’t call out the different layers of the structure. My guess is that (working out from the center) the gray center is a SiO2 fill, the yellow is the polysilicon channel, the blue is the tunnel dielectric, the green is a charge trapping layer, the next blue is the gate dielectric, but I don’t know what the pink layer would be. The control gates are the red horizontal layers, and the insulator between bits, a horizontal SiO2 layer, is not shown in order to add clarity.
You might think that manufacturing a vertical NAND string looks extraordinarily difficult, and you are right. It’s tough to etch a hole sufficiently deep and narrow, and sufficiently consistent from top to bottom. It’s also very tough to keep the width of the hole consistent while going through layers of very different materials. A lot of research has been devoted to managing this. Applied Materials believes that it has a good process to control all of these, but the real proof will be seen once someone enters true mass production of 3D technology.
In the next post we will explore how other companies, notably Hynix and Samsung, take a different approach to manufacturing a vertical NAND string.
This post is a part of a series called What is 3D NAND? Why do we need it? How do they make it? that was published in weekly segments during the fourth quarter of 2013 on The Memory Guy blog. The different sections are listed below, with a hot link to each section.
- Why Do We Need 3D NAND?
- What Is a 3D NAND?
- Making a Vertical NAND String
- An Alternative Kind of Vertical 3D NAND String
- How Do You Access the Control Gates?
- Benefits of Charge Traps over Floating Gates
- How Do You Erase and Program 3D NAND?
- 3D NAND’s Impact on the Equipment Market
- Who Will Make It and When?
Click on any of the above links to learn more about 3D NAND technology.