FMS (formerly the Flash Memory Summit) announced on July 24 that a research team from Kioxia will receive the award for inventing 3D NAND flash at FMS: the Future of Memory and Storage, on August 6 in Santa Clara, California. We hope to see you there as the award is being presented to a member of that team.
The team has five members, shown below: Hideaki Aochi, Ryota Katsumata, Masaru Kito, Masaru Kido, and Hiroyasu Tanaka.
This invention not only saved NAND from hitting its scaling limit at 15nm, which would have forever prevented any further cost reductions, but it also paved a path for other technologies to use a similar approach to reduce chip costs.
In other words, it allowed for Moore’s Law scaling to continue, and that’s a really big deal.
Few people realize that Gordon Moore actually mentioned the importance of such ideas in his 1975 follow-up to the 1965 paper that was the genesis of Moore’s Law. In his 1975 paper Moore argued that a chip’s transistor count increase, which led to cost reductions, was the result of three factors:
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- Shrinking the transistor size
- Increasing the die area
- “Cleverness”
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3D NAND’s approach ignored the first two – it was simply cleverness that provided an altogether new path for increasing a chip’s bit count and subsequently reducing bit costs. That’s why Toshiba, Kioxia’s predecessor, decided to name this process “BiCS” for “Bit Cost Scaling.”
In honor of 3D NAND and the team who invented it, The Memory Guy blog will refresh a series of posts I wrote in 2013 that explains why 3D NAND is needed and how it is manufactured. One update will be posted every week for the next nine weeks.
I hope that readers will get a lot out of this series. I had fun researching and writing it. 3D NAND is an amazing technology, and a considerable departure from the original planar NAND, as well as from other semiconductors.
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