A very unusual side effect of the move to 3D NAND will be the impact on the equipment market. 3D NAND takes the pressure off of lithographic steps and focuses more attention on deposition and etch. The reason for going to 3D is that it provides a path to higher density memories without requiring lithographic shrinks.
This sounds like bad news for stepper makers like ASML, Canon, and Nikon while it should be a boon to deposition and etch equipment makers like Applied Materials, Tokyo Electron, and Lam Research.
In its summer 2013 V-NAND announcement, Samsung explained that it would be using 40nm lithography to produce NAND at an effective process of 10nm. This follows from the argument made in an earlier post that the process would be effectively shrunk by the square root of the number of layers. Although Samsung is using 24 layers, it appears that only 16 of these layers are for memory bits, with the others serving as select gates and such.
Semiconductor makers try their best to re-use process equipment as much as possible when they switch from one generation to the next. This helps them control CapEx (capital expenditure) costs. The move to 3D is expected to be more costly than prior flash generations, since a significant investment will need to be made in deposition and etch equipment to keep the converted fab running at its peak capacity. In fact, some lithography tools may be decommissioned from these fabs since they may no longer be of any use.
This post’s first graphic (a slide presented by Applied Materials) compares the incremental lithography and other investments required to migrate to a couple of generations of planar NAND flash (3X, 1X, & 1Y, referring to the process in nanometers) and to the first generation of 3D NAND. (Hint: If you right-click the graphic and select “Open in New Window” you can toggle back & forth between the full chart and this text using Alt-Tab.)
The blue chart on the left of this graphic shows the incremental lithography investment, and the green charts to its right show tool investments for thermal processes (annealing) and ion implant, chemical vapor deposition (CVD), and plasma etch. It’s pretty clear that the green graphs on the right are increasing from one generation to the next, while the blue chart on the left is decreasing. Applied Materials compiled this chart to tell us that lithography spending is headed down while other processing equipment expenditures are on their way up, at least for NAND flash.
After this post was originally published I spoke with ASML, the leading lithography tool maker, and learned a very different viewpoint on this matter, which the company illustrated with this chart of its own, which is this post’s second graphic. This chart doesn’t represent any single process, rather it is based on the average of the company’s customers and the average of their process geometries.
The chart’s horizontal axis shows three different processes and their years of mass production: 2x 2D is a planar (2D) process in the 20-29nm range. 1x 2d is a planar process smaller than 20nm, and 5x-24 3D represents a 3D NAND with 24 layers produced using 5Xnm lithography.
The vertical axis shows the number of lithography passes: how many times must the wafer be exposed by a certain type of scanner? (Keep in mind that these numbers are a combination of typical numbers for the average vendor, and don’t represent any particular vendor’s process.)
Each column is broken down to show the tool type that is required. The bottom dark gray is the i-Line tool, the oldest and least expensive scanner in a typical NAND flash fab. These are generally used for the peripheral CMOS circuitry which can be produced using larger features than the memory bits themselves. The number of passes over these tools changes very little from process to process. The medium-gray portion represents the Kr-F (Krypton-Fluorine) scanner, which is also relatively inexpensive and its use also increases slightly from process to process. The lightest gray section is a more costly ArF (Argon-Fluorine) stepper, which is used, on average, for two passes for any of these processes. At the top is the blue portion of the column, representing immersion ArF lithography tools, the costliest scanner in the fab, which is reserved for critical mask layers. The ArF tool is used for only seven process steps in both the 2Xnm and 1Xnm process, but this number jumps to ten steps for 3D.
ASML has told me that some of these critical steps are unique to 3D NAND, like making the hole, cutting the slits, and etching the vias to the stairsteps.
The third graphic is a chart that SanDisk shared during an analyst meeting in May. The turquoise columns illustrate the per-wafer cost of tooling a brand new fab for each process node. The shorter maroon columns represent the per-wafer cost to convert a fab from the prior generation to the current process generation.
According to SanDisk, each upcoming transition, starting with 19nm (the company’s “1X” technology) will be more costly than prior generations, since so many new tools will need to be purchased, tools that were not required for any of the company’s prior flash generations. The migration from SanDisk’s 1X (19x26nm) to its 1Y (19×19.5nm) process requires the addition of a Hi-k gate dielectric. Neither Toshiba nor SanDisk have disclosed the process these companies plan to use for their 1Z transition, but the chart indicates that this transition will be more costly than preceding transitions. It’s safe to assume that migration to 3D will require an even larger complement of new materials tools at a significant increase in cost. This will eat into the company’s profits.
It isn’t yet clear whether 3D NAND makers will try to use lithography to compete against each other. The reason why is that the industry doesn’t yet know how closely 3D NAND columns can be placed to each other. Toshiba states that its BiCS column can be made thinner than Samsung’s TCAT. The limitation to any column’s width has a lot to do with how thinly the sidewalls can be deposited onto the sides of the trench, and how extreme of an aspect ratio can be etched into the stacked layers.
The aspect ratio problem may be addressed by making the layers thinner, but this is a new process that has never before been put into production, so nobody knows how thin those layers can be made in a production environment. BiCS layers can be made thinner than the layers in TCAT since TCAT has to squeeze two charge trap layers and one tantalum layer between every oxide layer of the stack, so BiCS is likely to support more layers at a lower aspect ratio for the hole.
Unfortunately, making the layers thinner will probably lead to other problems. The thickness of the conductive polysilicon or tantalum layer defines gate length in the string: The thinner the layer, the shorter the gate. Thinning the conductive layer will also increase its resistance and that could limit where and how this trick can be used.
Making the insulating layers thinner can also lead to issues since these layers need to isolate the wordlines from each other. As the insulating layer is thinned the capacitive coupling between wordlines increases, leading to crosstalk and disturb issues.
One additional challenge is that shrinking the width of the column will mean that the NAND string will have a thinner channel, and this may limit current to the point that the cells on the string no longer work.
All in all, there are simply too many unknowns about 3D processes to precisely predict whether lithography can be used to pack even more bits onto a wafer.
One interesting side effect of the transition to 3D NAND will be that DRAM and NAND wafer fabrication plants (“fabs”) will diverge significantly from each other. Most NAND makers (with the exception of Toshiba and SanDisk) also make DRAM chips, and today these NAND/DRAM manufacturers tend to build a new fab but wait until the last minute to decide whether the new fab will be used to manufacture NAND flash or DRAM. Although there were early attempts over a decade ago to make fully-fungible fabs that could switch rapidly and frequently between NAND and DRAM production, manufacturers found that the equipment balances of these two technologies were too different from each other, resulting in idle equipment. The depreciation of this equipment would still be counted against costs, increasing the cost structure of the fab, and since both NAND and DRAM are highly cost sensitive this approach was abandoned.
Future 3D NAND fabs will be tooled for a large number of deposition and etch steps, and few lithography steps, whereas DRAM fabs’ tooling costs will continue to be dominated by lithography, resulting in fewer and fewer commonalities between DRAM and 3D NAND fab tooling. In the end, very few manufacturers will consider converting a fab from one technology to the other.
This brings us to the question of who the manufacturers are, which will be the topic of the next (and final) post of this series.
This post is a part of a series called What is 3D NAND? Why do we need it? How do they make it? that was published in weekly segments during the fourth quarter of 2013 on The Memory Guy blog. The different sections are listed below, with a hot link to each section.
- Why Do We Need 3D NAND?
- What Is a 3D NAND?
- Making a Vertical NAND String
- An Alternative Kind of Vertical 3D NAND String
- How Do You Access the Control Gates?
- Benefits of Charge Traps over Floating Gates
- How Do You Erase and Program 3D NAND?
- 3D NAND’s Impact on the Equipment Market
- Who Will Make It and When?
Click on any of the above links to learn more about 3D NAND technology.