This week both the Toshiba-Western Digital team and Samsung disclosed details of their 64-layer 3D NAND designs at the IEEE’s International Solid-State Circuits Conference (ISSCC). The Memory Guy thought that it would be interesting to compare these two companies’ 64-layer chips against each other and against the one that Micron presented at last year’s ISSCC.
Allow me to point out that it’s no easy feat to get to 64 layers. Not only must the process build all 64 layers (or actually pairs of layers plus some additional ones for control) across the entire 300mm wafer with high uniformity and no defects, but then holes must be etched through varying materials from the top to the bottom with absolutely parallel sides at aspect ratios of about 60:1, that is, the hole is 60 times as deep as it is wide. After this the fab must deposit uniform layers of material onto the sides of these skinny holes without any variation in thickness.
None of these processes have ever been used to build any other semiconductor — it’s all brand new. This is what makes 3D NAND so challenging, and it’s why the technology is already 3 years behind its original schedule.
It’s not easy to tell from the conference papers whether or not the chips use the String Stacking approach detailed in another Memory Guy blog post. Nobody mentioned that technique. In its 2016 ISSCC paper Micron didn’t even disclose the number of layers in its chips, but the company revealed that it was a 64-layer part during a recent analyst conference and also showed a cross-section photo that revealed string stacking. My guess is that the Toshiba-WD design uses string stacking as well, but Samsung’s paper indicated that its chip did not use this approach.
Samsung instead decided to make the layers 11% thinner than those of its prior-generation products. This introduced a new set of problems: Thinning the wordline layers increased their resistance. Thinning the dielectric between them increased coupling, leading to more noise and interference while degrading retention. There were also power and loading issues that stemmed from doubling the chip’s density.
The bulk of Samsung’s paper detailed the novel techniques the researchers developed to get around these new issues. The write cache was converted to a pipelined design to accelerate write cycles. An annealing pulse is used to remove stray holes from the charge trap and improve retention. Reads are classified using a more sophisticated “Valley Tracking” scheme to accommodate drift.
Toshiba’s paper focused on reducing the die area by breaking apart the address decoders as well as improving speed and error rates by using a new shielded-bitline scheme.
How do the three products compare against each other? The table below provides a good idea of that. I used parentheses to indicate parameters that were not disclosed but that are likely:
|Cell Type||Floating Gate||Charge Trap||Charge Trap|
All three use 64 layers and 3 bits/cell effectively, yet Micron’s Gb/mm² is higher than either of the others thanks to the fact that Micron manufactures the chip’s CMOS logic circuits underneath the memory array, while its competitors put the logic alongside the array.
None of this really matters, though, until all three companies bring these products to mass production. It’s unclear at this point when that will actually occur.
Interestingly enough, all three papers started out with an explanation of why the transition to 3D NAND was necessary. Given the high technical competence of the audience, and given the fact that Toshiba introduced the 3D NAND concept over ten years ago, it is puzzling that the researchers would take the time to tell the audience something they certainly must already know.
Those who would like to gain a better understanding of 3D NAND are welcome to read the Memory Guy series: What is 3D NAND? Why do we need it? How do they make it?
Those who need a deeper understanding can contact Objective Analysis for custom consulting on this exciting technology.
16 thoughts on “64-Layer 3D NAND Chips Revealed at ISSCC”
At Micron’s analysts day they disclosed their part is 64 layers and from a cross section they showed you can see it uses string stacking.
Many thanks for pointing that out. I haven’t watched the Micron Analyst Day video yet.
Page 18 of the Micron presentation shows 64 layers and page 22 shows the cross section where the stacking is evident.
Also on page 18 Micron shows that 32L 3D NAND is >30% cheaper than 16nm planar. I have arguments with people all the time who claim 3D NAND is more expensive than 2D and I say it isn’t, Micron’s disclosure is right in-line with my cost modeling.
The whole reason that 3D NAND was conceived was to make something cheaper than planar, and that should be the case at some point. Two things appear to be getting in the way, though, the bigger of which is yield. This will be solved in time.
The other is the fact that the stairstep, which is intended to be a single-exposure process, actually requires a number of passes through the scanner. This too will be solved. The only question is when.
I agree the stair step is multiple masks. In my view the stair steps per mask is going up but the number of layers is going up too and I believe it will always be a multiple mask process. I take that into account in my modeling.
I also agree that yields have been lower than 2D NAND although they are improving and Micron is now claiming “mature yield” on 32 layer TLC (slide 21) and they show a really good yielding 64 layer wafer on the same slide. Granted that is probably one of the best yielding 64 layer wafers they have gotten but my information is the 32 layers yields are now good and I also take yield into account in my modeling.
32 layer has >2x the bit density of 2D NAND so wafer cost and yield effects would have to be >2X to offset the bit density. In my view the yield is now sufficient for 32 layers costs to be less than 2D NAND and that is consistent with what Micron is saying on slide 18.
Interesting comments. Is there any intrinsic reason why the 3 CT suppliers can’t get to CuA?
I have heard that the charge trap material creates stresses that CMOS can’t tolerate. In other words, you can’t put a charge trap over CMOS.
Perhaps others understand this better than I do and can offer a more in-depth explanation.
Hi Jim – I find your analysis interesting but a little confusing. Could it be inferred from your math that each die has ~64GB capacity and on average you can make ~700 dies per wafer, which means each wafer has roughly 40TB to 45TB of storage. Using the low end of that range and assuming 100% of the wafer capacity is converted to 3D NAND capacity, then this would imply a whopping ~62 exabytes of NAND supply each month. Is that in the right ball park or am I missing something big here?
The Toshiba and Samsung chips are indeed 64GB, and the Micron chip is 96GB. With these die sizes gross dice per wafer should be 477 for Samsung, 466 for Toshiba, and 337 for Micron, so your estimate’s about double what it should be.
Gross TB/wafer should be 30.5 for Samsung, 29.8 for Toshiba, and 32.3 for Micron. That’s only about 30% lower than your estimate.
A 100K wafers/mo fab would generate about 3 exabytes/month. There aren’t that many fabs like this, probably 5 or less, so 15 exabytes/month.
Monthly shipments in 2017 were about 11EB/month, growing at about 45% per year, so this year should average about 15EB/month.
It works out.
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