Search Results for: Hybrid

Intel to Use Micron Hybrid Memory Cube

Micron: "Bursting Through The Memory Wall"Intel and Micron today announced that the new version of Intel’s Xeon Phi, a highly parallel coprocessor for research applications, will be built using a custom version of Micron’s Hybrid Memory Cube, or HMC.

This is only the second announced application for this new memory product – the first was a Fujitsu supercomputer back in November.

For those who, like me, were unfamiliar with the Xeon Phi, it’s a module that uses high core-count processors for problems that can be solved with high degrees of parallelism.  My friend and processor guru Nathan Brookwood tells me Continue reading

Micron Samples Hybrid Memory Cube

Close-Up of Micron's Hybrid Memory CubeToday Micron Technology announced that it is sampling the Hybrid Memory Cube (HMC) a DRAM packaging technology that it has been working on with the HMC Consortium.

Micron has been pushing to rapidly advance the HMC’s development and seems to have reached this point in an impressively brief time, given the complexity of the technology.  It has only been two years since the first public appearance of the HMC at the 2011 Intel Developer Forum.

Some pretty advanced technology was used to make this product.  DRAM processes are not very good at Continue reading

Hybrid Memory Cube Making Progress

Conceptual Cutaway Drawing of the Hybrid Memory CubeOn Tuesday the HMC Consortium (that’s short for “Hybrid Memory Cube”) announced that members have agreed upon a specification.  The consortium has been moving rapidly, meeting its targets despite the revolutionary nature of the interface.

As a reminder, this technology stacks multiple DRAMs in a single package with a logic chip at the base of the stack that performs all the signalling to the rest of the system.  Signals between the DRAMs and logic chip use through-silicon vias (TSVs) as interconnections.  This allows the technology to deliver 15 times the performance of DDR3 at only 30% of the power consumption.  The Memory Guy first posted about the HMC in late 2011.

The consortium explains that the HMC interface already has 100 adopters, and that a few Continue reading

WIOMING: Another Spin on the Hybrid Memory Cube

ST-Ericsson & CEA-Leti WIOMING Multichip ModuleAt a Conference in San Francisco today (Tuesday December 13 ) ST-Ericsson and CEA-Leti presented a paper on something the companies called a: “Breakthrough 3DIC with Wide I/O Interface.”

This product appears to be a variation on the Hybrid Memory Cube, or HMC concept detailed in a prior post.

Remember that the HMC stacks a number of DRAM chips atop a logic chip.  The memories store data and communicate to the logic chip through thousands of through-silicon vias (TSVs) while the logic chip handles communications with the outside world. Continue reading

IBM to Build Micron Hybrid Memory Cube

Conceptual Cutaway Drawing of the Hybrid Memory CubeIn a December 1 press release IBM announced that the company will be manufacturing Micron Technology’s Hybrid Memory Cube (HMC) which IBM claims to be “the first commercial CMOS manufacturing technology to employ through-silicon vias (TSVs).”

This device is one that Altera, Intel, Micron, Open Silicon, Samsung, and Xilinx have all presented recently as a plausible solution to the difficulty of increasing the speed of DRAM/processor communications.  The Hybrid Memory Cube Consortium (HMCC) website offers a deep dive into the details of the consortium and the technology.

Continue reading

UPMEM Processor-in-Memory at HotChips Conference

UPMEM DIMMs in a ServerThis week’s HotChips conference featured a concept called “Processing in Memory” (PIM) that has been around for a long time but that hasn’t yet found its way into mainstream computing.  One presenter said that his firm, a French company called UPMEM, hopes to change that.

What is PIM all about?  It’s an approach to improving processing speed by taking advantage of the extraordinary amount of bandwidth available within any memory chip.

The arrays inside a memory chip are pretty square: A word line selects a large number of bits (tens or hundreds of thousands) which all become active at once, each on its own bit line.  Then these myriad bits slowly take turns getting onto the I/O pins.

High-Bandwidth Memory (HBM) and the Hybrid Memory Cube (HMC) try to get past this bottleneck by stacking special DRAM chips and running Continue reading

Valuable Memory Technical Resources

India Inst of Tech Hyderabad SealEver since moving to Silicon Valley some time ago The Memory Guy has worked with a number of impressively-talented engineers from India.  Some are educated in the US, while others are educated in India.  One university that produces excellent engineers is the Indian Institute of Technology, or IIT.

It comes as no surprise, then, to find a valuable resource produced by an IIT faculty member.  Dr. Sparsh Mittal, an assistant professor at IIT Hyderabad, reached out to me to share some papers that he thought might be of interest to Memory Guy readers. They were a few of roughly 40 papers that he has posted on his publications page.  He explained that he previously worked at Oak Ridge National Lab, in the US.

Dr. Sparsh has published several very comprehensive surveys on memory systems, both conventional and emerging, covering topics like DRAM reliability, NVM/Flash, ReRAM-based processing-in-memory, and the architecture of neural networks.  The web page lists 34 surveys, eight of them Continue reading

Is Intel Adding Yet Another Memory Layer?

Where the Piecemakers DRAM FitsAt the International Solid State Circuits Conference (ISSCC) last week a new “Last Level Cache” was introduced by a DRAM company called “Piecemakers Technology,” along with Taiwan’s ITRI, and Intel.

The chip was designed with a focus on latency, rather than bandwidth.  This is unusual for a DRAM.

Presenter Tah-Kang Joseph Ting explained that, although successive generations of DDR interfaces has increased DRAM sequential bandwidth by a couple of orders of magnitude, latency has been stuck at 30ns, and it hasn’t improved with the WideIO interface or the new TSV-based High Bandwidth Memory (HBM) or the Hybrid Memory Cube (HMC).  Furthermore, there’s a much larger latency gap between the processor’s internal Level 3 cache and the system DRAM than there is between any adjacent cache levels.  The researchers decided to design a product to fill this gap.

Many readers may be familiar with my bandwidth vs. cost chart that the Memory Guy has used to introduce SSDs and 3D XPoint memory.  The gap that needs filling is Continue reading

Memsys: A New Memory Conference

1999 White HouseSince I am the Memory Guy I hate learning that I missed something new and cool in the world of memories, but somehow I was unaware of last week’s Memsys conference in Washington DC until a participant notified me on Saturday that his paper: “Reverse Engineering of DRAMs: Row Hammer with Crosshair,” had been given the the best paper award.

Upon looking at the Memsys website it looks like a very intriguing academic conference.  about sixty papers were presented in eight interesting sessions:

  • Issues in High Performance Computing
  • Nonvolatile Main Memories and DRAM Caches, Parts I & II
  • Hybrid Memory Cube and Alternative DRAM Channels
  • Thinking Outside the Box
  • Improving the DRAM Device Architecture
  • Issues and Interconnects for 2.5D and 3D Packaging
  • Some Amazingly Cool Physical Experiments

in addition to a few apparently-fascinating keynotes.

Fortunately, all of the papers are Continue reading

Samsung’s Colossal 128GB DIMM

Samsung_128GB TSV RDIMMIn a November 25 press release Samsung introduced a 128GB DDR4 DIMM.  This is eight times the density of the largest broadly-available DIMM and rivals the full capacity of mainstream SSDs.

Naturally, the first question is: “How do they do that?”

To get all the chips into the DIMM format Samsung uses TSV interconnects on the DRAMs.  The module’s 36 DRAM packages each contain four 8Gb (1GB) chips, resulting in 144 DRAM chips squeezed into a standard DIMM format.  Each package also includes a data buffer chip, making the stack very closely resemble either the High-Bandwidth Memory (HBM) or the Hybrid Memory Cube (HMC).

Since these 36 packages (or worse, 144 DRAM chips) would overload the processor’s address bus, the DIMM uses an RDIMM protocol – the address and control pins are buffered on the DIMM before they reach the DRAM chips, cutting the processor bus loading by an order of magnitude or more.  RDIMMs are supported by certain server platforms.

The Memory Guy asked Samsung whether Continue reading