Intel and Micron today announced that the new version of Intel’s Xeon Phi, a highly parallel coprocessor for research applications, will be built using a custom version of Micron’s Hybrid Memory Cube, or HMC. This is only the second announced application for this new memory product – the first was a Fujitsu supercomputer back in … Continue reading “Intel to Use Micron Hybrid Memory Cube”
Today Micron Technology announced that it is sampling the Hybrid Memory Cube (HMC) a DRAM packaging technology that it has been working on with the HMC Consortium. Micron has been pushing to rapidly advance the HMC’s development and seems to have reached this point in an impressively brief time, given the complexity of the technology. … Continue reading “Micron Samples Hybrid Memory Cube”
On Tuesday the HMC Consortium (that’s short for “Hybrid Memory Cube”) announced that members have agreed upon a specification. The consortium has been moving rapidly, meeting its targets despite the revolutionary nature of the interface. As a reminder, this technology stacks multiple DRAMs in a single package with a logic chip at the base of … Continue reading “Hybrid Memory Cube Making Progress”
At a Conference in San Francisco today (Tuesday December 13 ) ST-Ericsson and CEA-Leti presented a paper on something the companies called a: “Breakthrough 3DIC with Wide I/O Interface.” This product appears to be a variation on the Hybrid Memory Cube, or HMC concept detailed in a prior post. Remember that the HMC stacks a number of … Continue reading “WIOMING: Another Spin on the Hybrid Memory Cube”
In a December 1 press release IBM announced that the company will be manufacturing Micron Technology’s Hybrid Memory Cube (HMC) which IBM claims to be “the first commercial CMOS manufacturing technology to employ through-silicon vias (TSVs).” This device is one that Altera, Intel, Micron, Open Silicon, Samsung, and Xilinx have all presented recently as a … Continue reading “IBM to Build Micron Hybrid Memory Cube”
This week’s HotChips conference featured a concept called “Processing in Memory” (PIM) that has been around for a long time but that hasn’t yet found its way into mainstream computing. One presenter said that his firm, a French company called UPMEM, hopes to change that. What is PIM all about? It’s an approach to improving … Continue reading “UPMEM Processor-in-Memory at HotChips Conference”
Ever since moving to Silicon Valley some time ago The Memory Guy has worked with a number of impressively-talented engineers from India. Some are educated in the US, while others are educated in India. One university that produces excellent engineers is the Indian Institute of Technology, or IIT. It comes as no surprise, then, to … Continue reading “Valuable Memory Technical Resources”
At the International Solid State Circuits Conference (ISSCC) last week a new “Last Level Cache” was introduced by a DRAM company called “Piecemakers Technology,” along with Taiwan’s ITRI, and Intel. The chip was designed with a focus on latency, rather than bandwidth. This is unusual for a DRAM. Presenter Tah-Kang Joseph Ting explained that, although … Continue reading “Is Intel Adding Yet Another Memory Layer?”
Since I am the Memory Guy I hate learning that I missed something new and cool in the world of memories, but somehow I was unaware of last week’s Memsys conference in Washington DC until a participant notified me on Saturday that his paper: “Reverse Engineering of DRAMs: Row Hammer with Crosshair,” had been given … Continue reading “Memsys: A New Memory Conference”
In a November 25 press release Samsung introduced a 128GB DDR4 DIMM. This is eight times the density of the largest broadly-available DIMM and rivals the full capacity of mainstream SSDs. Naturally, the first question is: “How do they do that?” To get all the chips into the DIMM format Samsung uses TSV interconnects on … Continue reading “Samsung’s Colossal 128GB DIMM”
