Contributor Ron Neale returns to The Memory Guy blog with a deeper analysis of the University of Lancaster’s ULTRARAM, which was first announced relatively recently, in early 2020. This post includes his revealing interchange with the university’s Professor Manus Hayne, a key member of the ULTRARAM program, in which the professor indicates that GaAs ICs and Chiplets might be the way ahead for this technology.
Ron tells me that this is the first mention that he is aware of for plans to create compound semiconductor memory ICs and chiplets.
A relatively new challenger, the triple barrier resonant tunnelling (TBRT) non-volatile memory, has joined the ranks of emerging memory technologies. It has been named by its developers at Lancaster University as ULTRARAM.
Unlike many of the emerging memory technologies vying for mainstream acceptance, this one is different in a number of ways. It has an elegance which reaches to the leading edge and heart of modern solid state quantum physics, with a well-defined model of operation. No secret sauces or legerdemain just the magic of quantum mechanics, with memory characteristics that raise the possibility that it might be able to serve as a universal memory, meeting the speed/power requirements of SRAM/DRAM at one end of the memory spectrum and as an NV data store at the other end.
As you will find from my correspondence with a member of the development team, in the future ULTRARAM might even take peripheral memory technology in a radical new direction away from silicon towards new compound material based integrated circuits, with memory chiplets as possible initial ULTRARAM memory products.
A Simple Overview
ULTRARAM has a similar configuration to a flash memory cell, with a control gate above a floating gate above the transistor channel. In Flash each of these is isolated from the layer below with layer of SiO2. As shown in the simple illustration below, the oxide barrier which separates the floating gate from the channel of a Flash memory is replaced in ULTRARAM by three thin tunnelling barriers.
For the ULTRARAM the three barriers are part of an epitaxial stack consisting of floating gate, barriers and quantum wells. This cross-section is configured to show the compound semiconductor materials and thicknesses involved.
The spacing between the tunnelling barriers has been carefully tuned to create two quantum wells of unequal thickness, which separate the floating gate from the channel.
Quantum wells provide discrete new energy levels at the semiconductor band edge. Those levels relate directly to the physical width of the thin film which forms the well. The energy levels are represented by different colours (red, blue and green lines) in the band-gap illustration below:
This illustration contrasts the ULTRARAM to standard flash, which is shown in the box in the lower left side. Flash programs and erases by applying a high forward or reverse voltage to cause an electron to tunnel through the barrier oxide (shown as a yellow vertical bar).
The ULTRARAM uses a similar mechanism, however by varying the thickness of the material which forms each quantum well results in a misalignment of the principal energy levels marked (red, blue and green) for the as-fabricated device. Alignment and tunnelling is only possible when a unique single value of applied voltage aligns the levels for write and when reversed for erase as shown in the figure.
The application of the correct voltage allows electrons to move through the tunnelling barriers onto the floating gate or to be removed when the voltage is reversed. For write the red and blue energy levels align, while for erase the green and blue levels must be made to align, creating in each case the conditions required for electrons to tunnel and move through the barriers. When no bias is applied (upper left) the higher energy level of the quantum well in the centre of the diagram prevents any electron flow.
The need for the new gate complexity, vis-a-vis Flash, is outweighed by the advantages which come with it:
- Lower read and write voltages, almost an order of magnitude lower than Flash
- Lower write/erase power and lower write/erase times making it a non-volatile contender to replace DRAM/SRAM
- Retention times greater than are ever likely to be needed.
Write/erase voltages of equal to or less than ±2.7Volts are reported by the Lancaster team. The unique single operating read/write voltages offer the possibility of half signal orthogonal memory array addressing and configurations.
ULTRARAM does not have source and drain diffusions like some types of Flash memory, the metal for the contacts is applied directly to the transistor channel.
Readers will find a more formal and detailed explanation of the operation of ULTRARAM in the following references:
- ULTRARAM: A Low-Energy, High-Endurance, Compound-Semiconductor Memory on Silicon, Peter D. Hodgson, et. al., Wiley
- Room-temperature Operation of Low-voltage, Non-volatile, Compound-Semiconductor Memory Cells, Ofogh Tizno, et. al., Nature Scientific reports
- Simulations of Ultralow-Power Nonvolatile Cells for Random-Access Memory Dominic Lane & Manus Hayne, IEEE Transactions on Electron Devices, VOL. 67, NO. 2, February 2020.
- University of Lancaster Invents Yet Another Memory (UltraRAM), The Memory Guy blog
A More Detailed View
Professor Manus Hayne, Director of Research and Deputy Head of Physics Department at Lancaster University and technical lead for ULTRARAM development is now also tasked with the next steps required to move their memory to commercialisation. I put to Prof Hayne what I think are some of the hard questions he and the team will face in that commercialisation task.
The Lancaster University team have reported success with integrating ULTRARAM with silicon. One possible next step if they follow that path will be a need to convince one of the leading silicon memory fabrication companies to adopt the technology.
My starting point in our correspondence was the three bullet points that are linked to the near-term probability of success for emerging memory entrepreneurs, which I introduced in a recent Memory Guy blog post of mine. They are:
- The number of new materials and tools required, which are not already available in existing solid state fabrication facilities.
- The number of additional fabrication steps required
- The number of device characteristics where the explanation of the underlying mechanism is debatable and lacks a clear agreed science-based understanding.
The ULTRARAM memory, like any other memory array, requires peripheral interface circuits to access a memory array for read, write and erase, utilising conventional silicon technology, and fabrication as a BEOL to silicon processing.
In the context of the need to integrate with silicon, my first question for Manus Hayne was how he positioned ULTRARAM with respect to my first two bullet points. I also requested in his answer for him to include discussion of some aspects the BEOL process, which I see as potential problem areas, as sub-questions.
I asked for his responses to only the first two bullet points because, of all the emerging memory contenders, this one has the fewest problems with my third bullet point.
The First Sub-Question
As well as performance there are very significant differences between your ULTRARAM and competing emerging memories, as BEOL processes. The competing NV emerging memory devices are added as additional metallization or to existing metallization. ULTRARAM’s requirement for single crystal epitaxial films means the stack’s films must interface and match with a clean silicon surface, as illustrated in the cell cross section at the beginning of this post.
That would appear to mean that for your epitaxial process you will require on the pre-processed silicon wafers areas of clean single-crystal silicon surfaces, to be left untouched by processing, on which to deposit your GaSb-to-Silicon interface-matching buffer layer and memory array.
If those areas on the pre-processed silicon wafers that are reserved for the ULTRARAM array are oxidised, either deliberately or from atmospheric oxidation, some pre-epitaxial silicon surface cleaning process will be needed, with the potential to damage the existing silicon devices already on the wafers.
The Second Sub-Question
Your memory transistor does not have separate source and drain diffusions. The contact metallization makes direct contact with the InAs channel of the transistor, which your published work indicates is Ti/Au. I understand Cr and Ni can also be used to make Ohmic contacts, while in the early days triple metals were used.
Gold is a fast diffuser in silicon and it might be considered as an example of a material which by cross-contamination could either directly or indirectly affect the performance of the peripheral circuits already on the wafers being processed or other fabrication processes. Will Au or any of the other the new materials involved act to contaminate or compromise earlier silicon fabrication steps?
It also means your epitaxial stack will have to include the metallization link to the pre-processed peripheral, driver, decoder sense amplifiers. Will it be possible for you be able to utilise the metal systems already in use for source and drain contact metal?
What temperatures are required for your epitaxial processing or for any annealing-like fabrication steps or other environment conditions required for the stack and contact metal deposition?
All three of these are important questions because as a BEOL process there needs to be some assurance that the silicon devices already on the 12-inch wafers being processed will not be compromised.
Prof Hayne’s Surprising and Novel Reply
“If the monolithic integration of ULTRARAM with silicon CMOS is the way industry wants to go to exploit the performance of ULTRARAM, then the difficulties you mention will indeed have to be resolved.”
“However, we are presently pursuing an alternative route which provides a single answer to all your questions linked to silicon-based peripheral circuits.”
“The ‘new materials’ needed in ULTRARAM are only ‘new’ for silicon-based digital electronics. They are well known in optoelectronics/photonics/RF/power etc., which is an aspect of the semiconductor industry that is very successfully innovating across a range of devices and applications, some of which have shown huge compound annual growth rates (CAGRs.)”
“We have spent some time thinking about different options for the peripheral circuitry, i.e. the addressing logic: wafer bonding the array onto a Si chip that has the logic, co-integrating with Si CMOS (BEOL you suggest) and implementing the logic in the III-Vs. All of these options are challenging.”
“Wafer bonding a bare memory array with a huge number of connections required, e.g. 2001 for 1Mbit, does not seem very realistic. Regarding co-integration of III-Vs for digital electronics, III-V-based CMOS was an active area of research 10 years ago, so we decided that approach was not very satisfactory. As a result, we are working on a new approach to logic that is not CMOS-based (in any material system), i.e. does not involve pairs of nMOS and pMOS. We submitted a patent on that in June. The concept of this new type of logic device has been successfully modelled for two different III-V systems, and we are in the process of fabricating proof-of-concept devices.”
“I realise that this is quite radical, probably even more so than ULTRARAM itself. However, due to the extraordinary properties of ULTRARAM with low voltage operation, high endurance, non-destructive read and no refresh required, the peripheral circuitry is relatively straightforward. It only requires logic to address the array, voltages for read, program and erase, and current detection for readout (via a common ground). The logic will need to be integrated onto the ULTRARAM chip, but the electronics for the remainder could be provided externally. It may be that this lends itself well to the chiplet approach.”
I replied that this raises the question of the exciting possibility that the team might be heading in the direction of a new dedicated compound semiconductor integrated circuit fabrication line and compound semiconductor Chiplets.
“In the short term we plan to continue low to mid technology readiness level work in Lancaster, i.e. scaling devices, building up arrays, developing the logic.”
“For the next phase of latter-end research, pre-production and small scale/niche production at larger nodes (≤100 nm), we would not need a new fab, but could partner with existing open fabs. We are already making first enquiries in this direction, for both epitaxial and processing parts of ULTRARAM production. We don’t expect 100-nm ULTRARAM to be faster than DRAM, but it will be much more efficient, which is very attractive for several applications. This stage will inform the technical and financial viability of volume production at smaller nodes in a new III-V fab.”
Epitaxy Complexities and Film Thickness
At first glance the multilevel epitaxial ULTRARAM process looks complex, so I asked Prof Manus if he would briefly describe the type of additional new equipment which will be required for ULTRARAM processing and what will be the approximate capital cost?
“ULTRARAM fabrication comes in two parts. The first is the III-V semiconductor epitaxy, which is low cost by fab standards, and incorporates all the complexity of the semiconductor layers in a single technological step. Because of this the processing is simple. Our new (unpublished) self-aligned process for single devices has 10 steps and just 3 alignments, where all of the steps involve only the deposition of metal or dielectric layers or lithographical etching. This does not require any special equipment, and there is an established supply chain for III-V epitaxy.”
Another important process related question relates to film thickness and allowable tolerance in film thicknesses for each layer of the triple epitaxial memory stack. The thickness of the films appears to be an important variable in order to fix the levels in the quantum wells.
“We have already looked in to this*, modelling a variety of combinations of fluctuations in film thickness of one III-V lattice constant. This might not sound like much, but for the thinnest layers that can be 50%! The good news is that the properties of the TBRT are remarkably robust to such fluctuations.”
* Simulations of resonant tunnelling through InAs/AlSb heterostructures for ULTRARAM™ memory, Dominic Lane and Manus Hayne, 2021 J. Phys. D: Appl. Phys. 54 355104
For all emerging memory technologies scaling remains a potential stumbling block. I asked Prof. Hayne to provide an update with respect to scaling and the smallest area device the team have made and tested to date. In the literature 10µm x 10µm devices and simulations are reported. What are your predictions for scaling and what value of signal levels will you be dealing with at say the 20nm fabrication node?
“You are correct regarding the smallest devices fabricated to date. We are currently finalising our new process with less alignments and dry etching only, which will be suitable for scaling. We will shortly validate it using direct-write laser lithography before implementing it in our e-beam. We are aiming for large arrays at 100 nm, and ‘hero’ single 20-nm devices, limited by the capability of our e-beam.”
“Our channels are InAs, which has very high mobility, so we are not expecting a problem with undetectably-low readout currents.”
Tunnelling is an inherently rapid operation. An important question is: What has been achieved to date in realising that potential?
“Simulations show that the intrinsic switching speed, due to the resonant quantum tunnelling process is sub-ns, and this is supported by naively scaling the switching time of the fastest devices to date. The fastest devices we have made to date switched in 0.5ms for a 20micron gate size. Capacitance scaling 20nm implies 0.5ns.”
An important question is memory array and interface design and I raised with Prof Manus the question of what the ideal target bit density for a first ULTRARAM based product chiplet or otherwise.
“We have a very compact (1T) memory and array design, so using a definition of F as the gate dimension we expect to achieve a cell size of 6F².”
Similarities to Flash
I asked if there are some preliminary ULTRARAM memory array designs especially in relation to the interface with silicon, and if the array design is similar to Flash memory?
“Yes, we have already published our array design, and also some preliminary results on 4-bit arrays that validated the array concepts and potential performance, such as very low disturb. The interface with Si has been discussed above.”
There is close similarity between the ULTRARAM cell and Flash. I asked if it is possible that this new memory could be a drop-in replacement for existing Flash array designs as far as the peripheral circuits are concerned, or because of the single value of write/erase voltages would orthogonal half-voltage write arrays be a practical use of ULTRARAM, giving access to individual devices in the array?
“Yes, ULTRARAM is basically a III-V version of flash with all its shortcomings addressed. Device readout is also the same, so it could be used as a data storage memory (NAND flash, bits in series), and some people have suggested that.”
“However, due to the very low cost per bit of NAND flash, we decided to go in the RAM direction, more like NOR flash (bits in parallel), but with DRAM performance.”
No Need for Forming
Other emerging memory competitors have had to deal with forming. An obvious question: Does the ULTRARAM require forming in its as fabricated state and what is the logic sate of the as-fabricated memory?
“ULTRARAM is a floating gate memory, just like flash. No forming is required.”
ULTRARAM’s Extreme Data Retention
The University’s claims for calculated retention are impressive and represent a unique selling point. In your team’s published works, the term “room-temperature operation of non-volatile, charge-based memory cells” is used, suggesting that elevated temperature operation has not been evaluated. This raises the question: “What is the operating temperature of the memory and what has been established from real device experience?”
“You are right that the calculated retention times are extremely long, which is due to the size of the potential barrier trapping the charge in the floating gate. This large barrier also implies excellent high temperature operation. However, we do not know what any unintended charge loss mechanisms are, i.e. at what temperature they kick-in, so there is no substitute for experiment here. To date all our tests have been at room temperature, but we will start testing at higher temperatures very soon.”
“This is probably not the point of your question, but nevertheless very interesting, is performance at very low temperatures, i.e. 4° K. To be viable, quantum computers will need a conventional computer in the cryostat to allow it to interface to the classical world, but conventional Si electronics cannot do this. We are pretty confident that ULTRARAM will work very well at low temperature, and its efficiency is very attractive for this application.”
Conclusion: Final Comments
I would like to thank Prof Manus Hayne for his time, forbearance and his willingness to answer all and any of my questions regarding ULTRARAM and providing pointers to the future.
Solving the problem of finding a universal memory is likely to result in what to us now might appear to be a very complex device. The easy routes appear to have been found wanting.
Perhaps rather than “Silicon Valleys”, success in the future might rest with “Compound Semiconductor Valleys” or the like, producing Chiplets and ICs.