Ron Neale returns to The Memory Guy blog to discuss a “Universal Law” about memory elements and selectors that was presented by CEA Leti at the IEEE’s 2019 IEDM conference last December.
At IEDM 2019 D. Alfaro Robayo et al presented a paper titled: Reliability and Variability of 1S1R OxRAM-OTS for High Density Crossbar Integration that had a rather interesting claim of a “Universal Law”. It is possible that some links to the past might help to provide an explanation for Continue reading “Observations on the “Universal Law” for NV Memory Cells”
At CES last week Micron Technology introduced a new DRAM. The company’s second 1Znm production part, this 16Gb chip is an early supporter of the new DDR5 interface, opening the door to higher speeds and lower power consumption.
The company’s first 1Znm DRAM is the LPDDR4 part pictured on the left, which started Continue reading “Micron Debuts 16Gb 1Znm DDR5 DRAM Chip”
Kioxia (formerly Toshiba Memory) has announced another setback to its production: there was a fire on January 7 in the Fab 6 facility of its main Yokkaichi campus.
According to a customer letter that was published by TechNews the fire was limited to a single tool and was rapidly extinguished. Although the news story is in Chinese, a picture of the letter is included, and that letter is in English.
Kioxia seems to be Continue reading “Kioxia Fire. Not Again!”
In this final part of a five-part series, contributor Ron Neale continues his analysis of selector technologies focusing on the nature of the mystery of Forming and a number of the many unanswered questions.
Any search for Forming-Free structures might find some help in the article by Antonin Verdy of Leti titled: Optimized Reading Window for Crossbar Arrays Thanks to Ge-Se-Sb-N-based OTS Selectors. This article also Continue reading “NV Memory Selectors: Forming the Known Unknowns (Part 5)”
Everyone knows that DRAM prices have been in a collapse since early this year, but last week DRAM prices hit a historic low point on the spot market. Based on data the Memory Guy collected from spot-price source InSpectrum, the lowest spot price per gigabyte for branded DRAM reached $2.59 last week. This is lower than the prior low of $2.62 last July, which equaled an earlier $2.62 record set in June, 2016. See the figure Continue reading “DRAM Prices Hit Historic Low”
In this fourth part of a five-part series, contributor Ron Neale continues his analysis of selector technologies, focusing on the nature of the mystery of Forming and a number of the many unanswered questions.
From the discussion and investigations outlined in the earlier parts of this series, there would appear to be a number of options to explain selector Forming, where on the first switching event the threshold switching voltage Continue reading “NV Memory Selectors: Forming the Known Unknowns (Part 4)”
Hprobe: a test equipment manufacturer based in Grenoble France, has cast its vote for MRAM to succeed in the emerging memory battle. It has created a piece of production test equipment dedicated to MRAM technology.
The company has developed a new perpendicular magnetic generator module that allows Continue reading “Hprobe’s Vote for MRAM”
Almost one year ago Tom Coughlin and The Memory Guy presented the findings of our first emerging memories report at the Storage Networking Industry Association’s (SNIA) Storage Developers Conference (SDC). The podcast of this presentation has just been made available on the SNIA website.
In the podcast, titled “The Long and Winding Road to Persistent Memories,” Tom and I reviewed leading emerging memory technologies as we had surveyed them for our report.
This is a highly visual presentation, so I would recommend following along with the slides, which can also be downloaded from the SNIA SDC website at HERE. That same page combines the slides and the podcast into a video, so if you’re able to, it might be a good idea to watch the video. If you’re driving as your listening to it, though, then please use the podcast instead!
In the time since that podcast was recorded Tom and I have updated the report to a 2019 edition, which can be Continue reading “Podcast: Storage Developer Conference 2018 – Emerging Memories”
In this third part of a five-part series, contributor Ron Neale continues his analysis of selector technologies focusing the nature of the mystery of Forming and a number of the many unanswered questions.
From Part 2 of this series it is very clear that only a detailed and accurate description of threshold switching will allow an assessment of what might be possible during the act of Forming, when the threshold voltage of a selector or memory (if the latter is fabricated in its amorphous state) is reduced in some cases by a factor more than 30% from its as-fabricated value. The problem is that there have been numerous attempts to account for the threshold switching mechanism. In Part 3 of this series I will briefly explore some of threshold switching options and search for any which might be used to account for Forming.
Threshold switching: The key.
If understanding what is happening during threshold switching is the key to what might be possible during that single cycle of threshold switching associated with selector Forming, then there is a possible converse connotation: If we really understand what is happening Continue reading “NV Memory Selectors: Forming the Known Unknowns (Part 3)”
This week’s HotChips conference featured a concept called “Processing in Memory” (PIM) that has been around for a long time but that hasn’t yet found its way into mainstream computing. One presenter said that his firm, a French company called UPMEM, hopes to change that.
What is PIM all about? It’s an approach to improving processing speed by taking advantage of the extraordinary amount of bandwidth available within any memory chip.
The arrays inside a memory chip are pretty square: A word line selects a large number of bits (tens or hundreds of thousands) which all become active at once, each on its own bit line. Then these myriad bits slowly take turns getting onto the I/O pins.
High-Bandwidth Memory (HBM) and the Hybrid Memory Cube (HMC) try to get past this bottleneck by stacking special DRAM chips and running Continue reading “UPMEM Processor-in-Memory at HotChips Conference”