Jim Handy

Monatomic PCMs: A New Direction

Ron NealeUntil now designers of PCM devices have tried to make PCM meet their expectations by experimenting with an almost infinite number of possible multi-element glass compositions, in order to tinker with or emphasise a particular composition-related device characteristic. The apparent advantage of this great variety of materials comes with the baggage of reliability and performance-compromising element separation, driven by the forces of electro-migration, electrostatic effects and phase separation.

Is it possible to cast aside the problems of the multi-element PCM compositions and look at the possibility of monatomic PCMs?  For a team at IBM, Zurich and Aachen University the answer is an unequivocal “Yes!” and recently they have published details of the remarkable progress they have made with amorphous antimony (Sb), as an initial candidate element. This research was published in a June 2018 paper in Nature Materials Letters titled: Monatomic phase change memory, by Martin Salinga et al, IBM and Aachen University).

A difficulty faces those venturing in this new direction: While it is possible to bring many elements to the amorphous state, they very quickly crystallize at room temperature and higher.  The IBM researchers used simulations to find that the keys to obtaining a stable amorphous state is to control the quenching rate and the volume of the sample. That part of the antimony research is underpinned by some very impressive simulations that use only about 200 atoms.

Here’s the issue that this approach Continue reading

Why are NAND Flash Fabs so Huge?

NAND Economies of ScaleMany readers have probably wondered why NAND flash fabs are so enormous.  Although DRAM fabs used to be the largest, running around 60,000 wafers per month, NAND flash fabs now put that number to shame, running anywhere from 100,000-300,000 wafers per month.  Why are they so huge?

The reason is that you need to run that many wafers to reach the optimum equipment balance.  The equipment must be balanced or some of it will be sitting idle, and with some tools costing $50 million (immersion scanners) you want to minimize their idle time to the smallest possible number.  I am sure that this is a tough problem, although I have never had to solve it myself.

The most important reason that so much attention is focused on this is that the cost of the wafer depends on the efficiency of the fab.  If you built a $13 billion NAND flash fab that produced 90,000 wafers per month instead of 100,000 wafers per month, then the amount of investment per wafer would be 10% higher.  That can make a significant difference to Continue reading

Extending the Write/Erase Lifetime of Phase Change Memory: Part 4 – The Possible Implications for 3D XPoint and Optane

Ron NealeThis is Part 4 of a series in the Memory Guy blog, which has been looking at some important detailed analytical work by a joint team at IBM and Yale University which might point to the way of achieving improved PCM endurance.  I want, in this final part, to focus on its possible implications for commercial PCM products.


When Intel and Micron first introduced 3D XPoint Memory the companies claimed that it would be 1,000 times as fast as flash memory with 1,000 times the endurance at ten times the density of standard memory (meaning DRAM).  Now that Intel’s XPoint-based Optane SSDs have been released and their specifications are public we can estimate what the technology’s endurance might be.

The table below, explained in another Memory Guy blog post, gives estimates of best-case endurance for the cells in the XPoint memory in Optane SSDs.  In other words, with a sophisticated enough controller, good DRAM buffering, and overprovisioning, all of which are techniques commonly used to extend the life of the media in a NAND flash SSD, the cell lifetime could be significantly lower than that shown in the last column of the table and the SSD would still provide the specified endurance.  (These techniques are explained in detail in an SSD Guy blog post series for anyone who is interested in understanding them.)

As the calculated Continue reading

Making Sense of Intel & Micron’s XPoint Breakup

Micron-Intel 3D XPoint Memory InternalsOn Monday, July 16, Intel and Micron announced the termination of the two companies’ 3D XPoint Memory development efforts.  The companies will complete development of the second-generation product after which the IMFT Lehi, Utah facility will continue to manufacture the product but the two companies will no longer co-develop new versions of the 3D XPoint Memory.

Most readers haven’t been watching this business as carefully as The Memory Guy, and are puzzled by the move.  I will share what I know in an attempt to make the decision a little clearer.

Three years ago in July 2015 the two companies held an event to launch 3D XPoint Memory technology.  This upcoming technology would be 1,000 times faster than flash, and provide 1,000 times the endurance, on a chip that was 10 times as dense as “Standard Memory,” which everyone was to infer was DRAM.  This last implied that the technology would sell for a lower price than DRAM, and that’s the most important way that a technology that’s slower than DRAM can gain acceptance in a Continue reading

Extending the Write/Erase Lifetime of Phase Change Memory: Part 3 – Failure Modes for the Threshold Switch

Ron NealeThis is Part 3 of a short Memory Guy series which continues to explore the possible future impact on PCM memory performance, especially write/erase endurance, building on the results of the IBM/Yale University analysis outlined in Part 1 and Part 2.


Part 3 of this series of articles triggered by the recently published PCM device analysis by a team from IBM/Yale University, moves to a look at its possible implications for the arsenic doped GST threshold switch.  Although the threshold switch was not part of the IBM/Yale work, the implementation of the call for bipolar operation of PCMs means there will be a requirement for a threshold switch whose durability matches that of the memory with which it will be associated in a memory array.

If the study’s finding for PCM can be applied to the arsenic-doped GST threshold switch which is used in today’s commercially-available PCM arrays then the threshold switch might just be the weak link that accounts for the poor endurance of commercial PCM memory arrays.

One little conundrum we must address is: Which Continue reading

Why DRAM is Threatened by SSDs

Memcon Slide on FlashConventional wisdom holds that SSDs will someday displace all HDDs, but in reality SSDs are proving to be more of a challenge to the DRAM market than to the HDD market.

Right now you are probably reviewing the date of this post to make sure it’s not dated April 1.  I assure you that this is the truth.  To understand it, though, you must look at a computer as a computer architect would, or, in other words, the way that an application program sees the memory/storage hierarchy.

To the application program there is no HDD and memory, there is only memory.  The Virtual Memory system, a part of the operating system, hides the difference between the two by moving code and data into DRAM as it is needed and back onto the HDD when it is no longer important, without telling the application program that it is moving anything around.  I like to tell people that the DRAM makes the HDD look fast, and the HDD makes the DRAM look big.

If you think of the DRAM as something that makes the HDD look fast, then additional DRAM should help to make the Continue reading

Extending the Write/Erase Lifetime of Phase Change Memory: Part 2 – A More Complete View of Element Separation

Ron NealeThis is Part 2 of a short Memory Guy series which will continue to explore the possible future impact on PCM memory performance, especially write/erase endurance, building on the results of the IBM/Yale University analysis outlined in Part 1.


After, in Part 1, summarizing the methodology my next step was to try to bring together in another simple diagram all the detail of the complexity of  the movement of the different elements of the phase change memory material at different locations within the memory cell which the IBM/Yale work has disclosed. Movement which leads to the conclusion that bi-polar operation would be means of extending PCM endurance.

In this post’s first diagram (below) the central region provides illustration of the paper’s unique PCM device structure: A high aspect ratio tapered cell lined with a metal conductor. With the two-state memory switching region located (red coloured) roughly at the centre of the taper.  This means that, Continue reading

How to Worsen a DRAM Shortage

Fuzhou Intermediate People's CourtIn an interesting twist to today’s ongoing DRAM shortage, the Fuzhou Intermediate People’s Court, Fujian Province, China today granted a preliminary injunction to prevent Micron’s Chinese subsidiaries from manufacturing, selling, or importing certain DRAM modules and solid state drives in China.

This injunction, according to a Micron press release, was filed without allowing Micron to present its defense, a process which Micron finds to be: “inconsistent with providing a fair hearing through appropriate legal processes and procedures.”

Micron’s customers in China will find that the DRAM shortage has just become even worse than it already was.  Before today China’s government was concerned enough about the shortage’s rising DRAM prices to have launched a price fixing investigation only one month ago.  One result of today’s decision will be that there will be less DRAM in China, and that will probably cause prices to rise even more.

What will be the impact to Micron?  I find it unlikely that this injunction is likely to change any DRAM maker’s business much during a shortage.  Any lack of Micron DRAM in China is likely to be serviced by Samsung and SK hynix, but since there’s a shortage, these companies will need to reduce their shipments outside of China to satisfy Continue reading

Extending the Write/Erase Lifetime of Phase Change Memory: Part 1- PCM Element Separation and Endurance

Ron NealeThis is the first of a new line-up of Memory Guy posts by Ron Neale.   In this 4-part series Ron takes a look at the recently-published analysis by a team from IBM and Yale University (Wiley: Communications of Advanced Materials, Volume 30, Issue 9, March 1, 2018 “Self-Healing of a Confined Phase Change Memory Device with a Metallic Surfactant Layer,” Xie et al) which has cast some new light on the complexity of the movement and element separation in phase change memory (PCM) device structures.


In this series of articles I will briefly review what I think is an important piece of work and its implications for the future of  PCM write/erase (w/e) endurance in commercial PCM memory arrays. Today’s production Phase-Change Memory, the basis of the Intel/Micron 3D XPoint Memory, wears out faster than expected.  This series will investigate some of the potential reasons for this discrepancy.

Back in 2016 a research team led by IBM claimed the world record for PCM w/e endurance of  greater than 2 x 10E12 cycles (ALD-based Confined PCM with a Metallic Liner Toward Unlimited Endurance, Proc IEDM 2016 ). As of today commercially available PCM memory arrays offer w/e endurance of some six orders of magnitude less.  The table below Continue reading

NAND Flash’s Layers of Layers of Layers

Bonding Wires on Stacked NAND FlashThe Memory Guy has found that some people get confused about the terminology surrounding flash “Layers” and “Levels,” Sometimes confusing the two, and often misunderstanding what each one means.  This post is meant to be a low-level primer to address that confusion.

There are actually three places where such terminology is used: The number of chips in a package, the number of conductor/insulator pairs in 3D NAND, and the number of voltage levels stored on any single bit cell within the chip.  I will address them in that order.

CHIP STACKING: Since the 1990s Both NAND and NOR flash chip makers have been stacking chips within a single plastic package.  Originally this approach was used to reduce the size of thin flip phones like the Motorola Razr by stacking an SRAM chip on top of NOR flash, but soon afterwards NAND chips began to use the same approach to get incredible storage capacities into a single IC package or eMMC, or into a microSD card format.  What began as 2-die stacks became 4, then 8, and now 16 high.  This post’s photo illustrates an 8-high stack.

Since the height of a standard plastic package for a chip is smaller than a stack of 16 full-thickness dice the wafers had to be Continue reading