Inotera recently announced earnings and posted an impressive 55% gross margin. Inotera is a pure-play DRAM maker, so it’s not too difficult to estimate the company’s process geometries based on its financials.
The Memory Guy thought it might be interesting to determine what I could from the 55% gross margin number.
First of all we can estimate Inotera’s manufacturing cost/GB based on the gross margin and an assumption about the company’s sales price/GB. The WSTS price per gigabyte for November was $7.83. Assuming that Inotera’s ASP was equal to this number, then at a gross margin of 55% the company’s cost/GB would have been $3.52.
Inotera’s acts as a foundry for Micron Technoogy. If Inotera sold to Micron at some lower price, then Inotera’s production costs would necessarily be proportionally lower to maintain the same gross margin.
Using the WSTS price: At a processed wafer cost of $1,600 (my rule of thumb) a $3.52/GB cost would require 454 8Gb dice to be produced on each wafer (dice per wafer or DPW) to achieve a cost of $3.52/GB. If 454 dice fit onto a wafer then the die size must be 135mm². For the 4Gb density the number would be 908 DPW, which you can achieve with a 70mm² die size.
For this exercise I assume that yield is close enough to 100% that the precise yield doesn’t matter. In high-volume semiconductor processing, yields are very close to 100%.
Based on these numbers and some clever algebra we can back out design rules. For either the 8Gb or 4Gb DRAM chip the average design rule for the company works out to 36nm.
I caution that there are some places where important errors could have crept into this calculation:
- Inotera sells a all of its output to Micron, and this is most likely sold at prices that are significantly lower than the average WSTS price per GB.
- My $1,600/wafer cost assumption is widely thought to be in error. Roughly the same number of people tell me that it’s too high as tell me that it’s too low. Based on these inputs I realize that I can’t really come up with a better number, no matter how bad it might be.
- I have assumed that Inotera’s designs are as efficient as DRAM designs usually are. Objective Analysis uses a number we call the Figure of Merit (FOM) and this analysis was based on an FOM of 13, which is typical of the dozens of DRAM die sizes we have analyzed over the past several years.
- Yields could be lower than 100%. Typically DRAM makers do a very good job on die yield, so the difference between 100% and Inotera’s actual yield should be small enough that this would not significantly impact any other part of these calculations.
What would be the impact of one of these numbers were in error?
- Assuming that Inotera’s price per gigabyte is lower than the WSTS $7.83 value, then the company would have to be using a tighter average process geometry than 36nm. The company’s investor presentations tell us that nearly all production during that quarter was 30nm, which might actually mean 30nm, although many DRAM makers use expressions like “30nm class” to categorize any process between 30nm and 39.999nm.
- If the wafer cost is lower than $1,600, then Inotera’s average process geometry would be less aggressive, and if the wafer cost is higher then processes would have to be more aggressive.
- If Inotera’s design is less efficient than its competition (a larger FOM) then the design rules would have to be more aggressive.
- Likewise, if yield is much lower than 100%, then the process would have to be more aggressive.
Still, in absence of anything else, this is a start. Anyone who would like to learn more about the actual formulas I used to arrive at these numbers is welcome to contact me.