Perhaps the oldest nonvolatile semiconductor memory type is the ferroelectric memory, which recently celebrated its 68th birthday. FRAM predates flash memory, EEPROM, and even UV-erasable EPROM. It’s even older than mask ROM, which wasn’t invented until 1967!
As a matter of introduction to the technology, FRAM, or ferroelectric memory, is a read/write nonvolatile memory technology that performs significantly better than Continue reading “FRAM Turns 68”
A couple of weeks ago NAND flash start-up YMTC announced the production release of its 128-layer 1.33 terabit QLC NAND flash chip. According to a DigiTimes article about the chip the company plans to claim a share of 8% of the global NAND flash market in 2021.
A number of my clients asked The Memory Guy about this, since YMTC doesn’t yet seem Continue reading “Can YMTC Really Win 8% of 2021’s NAND Flash Market?”
About a year ago a rumor was circulating that Samsung was unable to yield its sub-20nm products without using EUV for the finer processes. Since The Memory Guy doesn’t traffic in rumors I did not publish anything about this rumor at the time.
On March 25 the company verified the rumor, though, by issuing a statement that: “Samsung is the first to adopt EUV in DRAM production.” I found it interesting that the company turned something that was Continue reading “Samsung Admits to Needing EUV for Sub-20nm Nodes”
For more than a year The Memory Guy has been fielding questions about Micron’s QuantX products.
First announced at the 2016 Flash Memory Summit, this brand name has been assigned to Micron SSDs and DIMMs that use the Intel/Micron 3D XPoint Memory. Originally QuantX products were scheduled to ship in 2017, but Micron is currently projecting availability in 2019. My clients wonder why there have been these delays, and why Micron is not more actively marketing this product.
The simple answer is that it doesn’t make financial sense for Micron to ship these products at this time.
Within two weeks of the first announcement of 3D XPoint Memory, at the 2015 Flash Memory Summit, I knew and explained that the technology would take two years or more to reach manufacturing cost parity with DRAM, even though Intel and Micron loudly proclaimed that it was ten times denser than DRAM. This density advantage should eventually allow XPoint manufacturing costs to drop below DRAM costs, but any new technology, and even old technologies that are in low-volume production, suffer a decided scale disadvantage against DRAM, which sells close Continue reading “Where is Micron’s QuantX?”
There’s never been a more exciting time for emerging memory technologies. New memory types like PCM, MRAM, ReRAM, FRAM, and others have been waiting patiently, sometimes for decades, for an opportunity to make a sizeable markets of their own. Today it appears that their opportunity is very near.
Some of these memory types are already being manufactured in volume, and the established niches that these chips sell into can provide good revenue. But the market is poised to experience a very dramatic upturn as advanced logic processing nodes drive sophisticated processors and ASICs to adopt emerging persistent memory technologies. Meanwhile Intel has started to aggressively promote its new 3D XPoint memory for use as a persistent (nonvolatile) memory layer for advanced computing. It’s no wonder that SNIA, JEDEC, and other standards bodies, along with the Linux community and major software firms are working hard to implement the necessary standards and ecosystems to support widespread adoption of the persistent nature of these new technologies.
This post introduces a Continue reading “Emerging Memories Today: New Blog Series”
In an interesting twist to today’s ongoing DRAM shortage, the Fuzhou Intermediate People’s Court, Fujian Province, China today granted a preliminary injunction to prevent Micron’s Chinese subsidiaries from manufacturing, selling, or importing certain DRAM modules and solid state drives in China.
This injunction, according to a Micron press release, was filed without allowing Micron to present its defense, a process which Micron finds to be: “inconsistent with providing a fair hearing through appropriate legal processes and procedures.”
Micron’s customers in China will find that the DRAM shortage has just become even worse than it already was. Before today China’s government was concerned enough about the shortage’s rising DRAM prices to have launched a price fixing investigation only one month ago. One result of today’s decision will be that there will be less DRAM in China, and that will probably cause prices to rise even more.
What will be the impact to Micron? I find it unlikely that this injunction is likely to change any DRAM maker’s business much during a shortage. Any lack of Micron DRAM in China is likely to be serviced by Samsung and SK hynix, but since there’s a shortage, these companies will need to reduce their shipments outside of China to satisfy Continue reading “How to Worsen a DRAM Shortage”
Recently I have been hearing concerns that an impending wafer shortage might drive today’s DRAM and NAND flash shortages to epic proportions.
The Memory Guy doesn’t pretend to have any understanding of the raw wafer business, so I decided to consult Mark Thirsk, managing partner of Linx Consulting. Mark has been in this industry for quite a while and has a very good understanding of the ongoing status of the semiconductor materials supply chain.
Mark and I were on a panel together at SEMICON Korea in February, and he presented an interesting chart to compare the costs of different technologies. I asked him about this chart as well.
Here’s what Mark had to say:
“Our information is that major Continue reading “Wafer Shortages and DRAM/NAND”
Yesterday The Memory Guy learned of an amazing article in DigiTimes about a 3-6 week shutdown at Toshiba’s Yokkaichi NAND flash fab line. According to the story Toshiba’s production was shut down for 3-6 weeks accounting for a production loss of 100,000 wafers. Another article in PC Games N converted that to lost bytes and came up with the number 400,000 terabytes.
Some quick math shows the errors in both of these articles.
First of all, the wafer stoppage. The Toshiba/SanDisk Yokkaichi Joint Venture wafer fabrication complex processes a little over 2 million wafers per year. Divide that by 52 weeks and you find that’s about 40,000 wafers per week, so 100,000 wafers would be 2.5 weeks’ output, not 3-6 weeks.
The number of bytes that PC Games N published takes a little more math. According to TechInsights Toshiba’s 15nm 128Gb MLC chip has an area of 99mm². That gets you a little over 10TB/wafer. The company’s 48-layer TLC 256Gb part should produce about twice that. Yet, if you divide PC Games’ Continue reading “Did Toshiba REALLY Lose 3-6 Weeks’ Production?”
This week both the Toshiba-Western Digital team and Samsung disclosed details of their 64-layer 3D NAND designs at the IEEE’s International Solid-State Circuits Conference (ISSCC). The Memory Guy thought that it would be interesting to compare these two companies’ 64-layer chips against each other and against the one that Micron presented at last year’s ISSCC.
Allow me to point out that it’s no easy feat to get to 64 layers. Not only must the process build all 64 layers (or actually pairs of layers plus some additional ones for control) across the entire 300mm wafer with high uniformity and no defects, but then holes must be etched through varying materials from the top to the bottom with absolutely parallel sides at aspect ratios of about 60:1, that is, the hole is 60 times as deep as it is wide. After this the fab must deposit uniform layers of material onto the sides of these skinny holes without any variation in thickness.
None of these processes have ever been used to build any other semiconductor — it’s all brand new. This is what makes 3D NAND so challenging, and it’s why the technology is already 3 years behind its original schedule.
It’s not easy to tell from the conference papers whether or not Continue reading “64-Layer 3D NAND Chips Revealed at ISSCC”
According to a Business Korea article Samsung announced, during a June 14 investor event, plans to reduce its DRAM capital spending and shift its focus to 3D NAND.
The Memory Guy sees this as an unsurprising move. This post’s chart is an estimate of DRAM wafer production from 1991 through 2014. There is a definite downtrend over the past few years. The peak was reached in 2008 at an annual production of slightly below 15 million wafers, with a subsequent dip in 2009 thanks to the global financial collapse at the end of 2008. After a slight recovery in 2010 the industry entered a period of steady decline.
The industry already has more than enough DRAM wafer capacity for the foreseeable future.
Why is this happening? The answer is relatively simple: the gigabytes per wafer on a DRAM wafer are growing faster than the market’s demand for gigabytes.
Let’s dive into that in more detail. The number of gigabytes on a DRAM wafer increases according Continue reading “Understanding Samsung’s DRAM CapEx Cut”