Memory Applications – The Memory Guy Blog

Where is Micron’s QuantX?

For more than a year The Memory Guy has been fielding questions about Micron’s QuantX products.

First announced at the 2016 Flash Memory Summit, this brand name has been assigned to Micron SSDs and DIMMs that use the Intel/Micron 3D XPoint Memory. Originally QuantX products were scheduled to ship in 2017, but Micron is currently projecting availability in 2019. My clients wonder why there have been these delays, and why Micron is not more actively marketing this product.

The simple answer is that it doesn’t make financial sense for Micron to ship these products at this time.

Within two weeks of the first announcement of 3D XPoint Memory, at the 2015 Flash Memory Summit, I knew and explained that the technology would take two years or more to reach manufacturing cost parity with DRAM, even though Intel and Micron loudly proclaimed that it was ten times denser than DRAM. This density advantage should eventually allow XPoint manufacturing costs to drop below DRAM costs, but any new technology, and even old technologies that are in low-volume production, suffer a decided scale disadvantage against DRAM, which sells close Continue reading “Where is Micron’s QuantX?”

Super-Cooled DRAM for Big Power Savings

Recently Rambus announced that it was using cryogenic temperatures to boost computer performance in large datacenters. This research is being done in a joint project with Microsoft who is developing a processor based on Josephson Junctions.

This is an effort to provide a performance increases greater than can be attained through standard semiconductor scaling. The research project aims to attain improvements in cycle time, power consumption, and compute density, leading to better energy efficiency and cost of ownership (COO). The companies hope to gain side benefits of being able to squeeze more bits onto a DRAM chip thus reducing cost per bit, improving performance, and making DRAM chips less costly to produce.

The system these two companies are researching uses a memory system that is cooled to 77 degrees Kelvin (77°K) with a processor that operates at 4°K. To do this the memory system is bathed in liquid nitrogen while the processor is cooled by liquid helium. The temperatures are the boiling points of these two liquids.

Surprisingly, the fact that these two subsystems are in different Continue reading “Super-Cooled DRAM for Big Power Savings”

How NAND Flash Can Reduce DRAM Requirements

In a comment to a recent Memory Guy post I stated that NAND flash can reduce DRAM requirements, even in PCs. Some readers have told me that they wonder how this could be, so I will write this post to explain.

Some years ago Objective Analysis noticed that clever server administrators were able to use SSDs to reduce their systems’ DRAM requirements. Not only did this save them money, but it lowered power and cooling requirements as well.

Thinking that this might work on other kinds of computers, we commissioned a number of benchmarks to be performed on a PC.

These benchmarks found that after a system already has a certain minimum amount of DRAM, users can get a bigger performance boost by adding a dollar’s worth NAND flash than they can get by adding a dollar’s worth of DRAM.

In every case the minimum amount of DRAM was very small.

This benchmark data was compiled, written up, and explained in depth in the report: How PC NAND Will Undermine DRAM, which can Continue reading “How NAND Flash Can Reduce DRAM Requirements”

New Algorithm Dramatically Reduces Storage & Power Requirements

A lone inventor has developed a data compression algorithm that defies the theoretical “Shannon Limit“. The press hasn’t covered this recent news, even though it has dramatic implications. This is probably because the technique is so very arcane. The inventor is none other than the great-great-great granddaughter of the inventor of the tabulated punch card, Herman Hollerith.

The algorithm reduces most of the data while converting the remaining information into as many ones as possible. This not only shrinks storage requirements and costs, but in the case of flash memory, it also has an important impact on total power. Flash is erased by setting all bits to ones, and bits are written by either leaving them alone (one) or by changing them (zero). The fewer zeros in the code, the less energy required to change the bits. Energy is also saved during an erase, since fewer bits need to be brought back to the erased state.

To explain the algorithm in its simplest terms, a byte of data is evaluated. If it has more zero bits than one bits the byte is inverted and an index bit is set to reflect this fact. Next, the four bits on either side of the byte are evaluated and if one has more zeros than ones it is inverted and another index bit is set. This process continues until Continue reading “New Algorithm Dramatically Reduces Storage & Power Requirements”

Memory Issues in Space & Medical Applications

The Memory Guy was recently asked about using memories in a satellite. What would be a good technology to use in a space application?

The problem with space is that there is a lot of radiation. Radiation on the earth’s surface is lower because it is stopped by the atmosphere, but in space there is an abundance of radiation that interferes with most semiconductors. Radiation is also a concern in certain medical applications where a memory must maintain its contents while undergoing sterilization through irradiation. Experiments on conventional flash memories have shown data loss at only 2% of the Continue reading “Memory Issues in Space & Medical Applications”

Micron Announces Processor-In-Memory

During the Supercomputing Conference in Denver today Micron Technology announced its new twist on processing: A DRAM chip with an array of built-in processors.

Dubbed: “The Automata Processor” this chip harnesses the inherent internal parallelism of DRAM chips to support a parallel data path of about 50,000 signals to attain processor-DRAM bandwidth that can only be dreamed of using conventional DRAM interfaces. The processor is a Graph-Oriented architecture.

The chip lends itself to Continue reading “Micron Announces Processor-In-Memory”

NAND Flash at 35 Cents per Gigabyte

Last January at the Storage Visions Conference in Las Vegas (held every year just prior to CES) I asked the audience what they would do when NAND flash reached a price of 35¢ per gigabyte. My projection (the dotted red line on the chart at left) was that prices would reach that level by the end of the year.

My audience was shocked to hear such a low price!

Price declines open up new markets. It was time to think creatively, I said, because that’s where pricing would be by the end of 2012.

Well, I was wrong – according to Continue reading “NAND Flash at 35 Cents per Gigabyte”

Why DRAM Bit Growth will Suffer

It seems that DRAM makers are still unaware of the impact NAND flash will have on DRAM revenues. Even though many are paying a lot of attention to the impact of the Tablet PC on Notebook PC shipments, few understand that even a healthy notebook market will start to place a decreasing focus on the system DRAM in the near future.

The reason why is simple, and it’s explained in great detail in a report: How PC NAND will Undermine DRAM. In a nutshell, once a basic minimum DRAM requirement has been met, NAND flash yields a greater performance return per dollar than does DRAM. This is illustrated in the graphic to the left.

Forget about the fact that NAND flash is nonvolatile, and that it offers Continue reading “Why DRAM Bit Growth will Suffer”

NAND Flash Turns 25!

On April 3 Toshiba celebrated the 25th anniversary of NAND flash. The technology, developed by Toshiba researcher Fujio Masuoka, was not expected to succeed, as explained in Eli Harrari’s keynote for ISSCC in February.

Toshiba said in a release that the company’s “commemoration of the 25th anniversary of the invention of NAND flash will continue throughout 2012,” and will include “notable industry events and consumer participation.”

There is certainly reason to celebrate. This technology has grown faster than any semiconductor market in history, Continue reading “NAND Flash Turns 25!”

IEEE Spectrum: Did Bad Memory Chips Down Russia’s Mars Probe?

The IEEE Spectrum published an interesting article postulating that Russia’s recently-failed Mars probe may have suffered from bad memory chips. According to the Spectrum article the Russian government’s Official Accident Investigation Results faulted SRAMs:

The report blames the loss of the probe on memory chips that became fatally damaged by cosmic rays.

Both the main computer and the backup computer seem to have failed at the same time, Continue reading “IEEE Spectrum: Did Bad Memory Chips Down Russia’s Mars Probe?”