The Memory Guy has found that some people get confused about the terminology surrounding flash “Layers” and “Levels,” Sometimes confusing the two, and often misunderstanding what each one means. This post is meant to be a low-level primer to address that confusion.
There are actually three places where such terminology is used: The number of chips in a package, the number of conductor/insulator pairs in 3D NAND, and the number of voltage levels stored on any single bit cell within the chip. I will address them in that order.
CHIP STACKING: Since the 1990s Both NAND and NOR flash chip makers have been stacking chips within a single plastic package. Originally this approach was used to reduce the size of thin flip phones like the Motorola Razr by stacking an SRAM chip on top of NOR flash, but soon afterwards NAND chips began to use the same approach to get incredible storage capacities into a single IC package or eMMC, or into a microSD card format. What began as 2-die stacks became 4, then 8, and now 16 high. This post’s photo illustrates an 8-high stack.
Since the height of a standard plastic package for a chip is smaller than a stack of 16 full-thickness dice the wafers had to be Continue reading “NAND Flash’s Layers of Layers of Layers”
Since I am the Memory Guy I hate learning that I missed something new and cool in the world of memories, but somehow I was unaware of last week’s Memsys conference in Washington DC until a participant notified me on Saturday that his paper: “Reverse Engineering of DRAMs: Row Hammer with Crosshair,” had been given the the best paper award.
Upon looking at the Memsys website it looks like a very intriguing academic conference. about sixty papers were presented in eight interesting sessions:
- Issues in High Performance Computing
- Nonvolatile Main Memories and DRAM Caches, Parts I & II
- Hybrid Memory Cube and Alternative DRAM Channels
- Thinking Outside the Box
- Improving the DRAM Device Architecture
- Issues and Interconnects for 2.5D and 3D Packaging
- Some Amazingly Cool Physical Experiments
in addition to a few apparently-fascinating keynotes.
Fortunately, all of the papers are Continue reading “Memsys: A New Memory Conference”
In a November 25 press release Samsung introduced a 128GB DDR4 DIMM. This is eight times the density of the largest broadly-available DIMM and rivals the full capacity of mainstream SSDs.
Naturally, the first question is: “How do they do that?”
To get all the chips into the DIMM format Samsung uses TSV interconnects on the DRAMs. The module’s 36 DRAM packages each contain four 8Gb (1GB) chips, resulting in 144 DRAM chips squeezed into a standard DIMM format. Each package also includes a data buffer chip, making the stack very closely resemble either the High-Bandwidth Memory (HBM) or the Hybrid Memory Cube (HMC).
Since these 36 packages (or worse, 144 DRAM chips) would overload the processor’s address bus, the DIMM uses an RDIMM protocol – the address and control pins are buffered on the DIMM before they reach the DRAM chips, cutting the processor bus loading by an order of magnitude or more. RDIMMs are supported by certain server platforms.
The Memory Guy asked Samsung whether Continue reading “Samsung’s Colossal 128GB DIMM”
Wiley has recently published a new book by Betty Prince titled Vertical 3D NAND Technologies that is one to consider if you want to bring yourself up to speed on recent research behind today’s and tomorrow’s 3D memory technologies.
For those who haven’t previously encountered Dr. Prince, she is the author of a number of key books covering memory design and holds memory patents written over her 30-year career in the field.
The book provides capsule summaries of over 360 papers and articles from scholarly journals on the subject of 3D memories, including DRAM, NAND flash, and stacked chips.
These papers are organized into Continue reading “New Book: Vertical 3D Memory Technologies”
SanDisk has introduced an SD Card with a whopping 512 gigabytes of storage. Noting that SD Card capacities have increased by 1,000 times over the past ten years, from 512MB to 512GB, the company says that this product is aimed at professional HD videographers (who can justify its $800 price) allowing them to shoot Raw-format footage without shutting their cameras off, which could potentially allow them to miss a magic moment.
To The Memory Guy this represents an amazing piece of packaging technology. Let’s see why:
In 2003 SanDisk’s 512MB card contained Continue reading “SanDisk’s Amazing 512GB SD Card”
On Tuesday the HMC Consortium (that’s short for “Hybrid Memory Cube”) announced that members have agreed upon a specification. The consortium has been moving rapidly, meeting its targets despite the revolutionary nature of the interface.
As a reminder, this technology stacks multiple DRAMs in a single package with a logic chip at the base of the stack that performs all the signalling to the rest of the system. Signals between the DRAMs and logic chip use through-silicon vias (TSVs) as interconnections. This allows the technology to deliver 15 times the performance of DDR3 at only 30% of the power consumption. The Memory Guy first posted about the HMC in late 2011.
The consortium explains that the HMC interface already has 100 adopters, and that a few Continue reading “Hybrid Memory Cube Making Progress”
In a new cross-disciplinary effort, researchers have developed a novel approach to attach bonding wires to stacks of memory chips. The new technique, being called a “breakthrough” by its developers, promises to allow chips to be stacked to several times their current 8-chip and 16-chip heights.
At issue is the challenge of precisely bonding wires a fraction of the diameter of a human hair over great distances without their inadvertently coming into contact with their neighbors to create a short circuit. Such a short could destroy one or more of the chips in the stack, rendering the entire stack useless. The mechanical means of attaching these wires, although highly sophisticated, still has significant issues, that limit the economics of higher stacks.
Researchers at the Berea University of Geology (BUG) in Berea, Kentucky, noticed that certain Continue reading “New Memory Bonding Technique Shows Promise”
Today I saw an announcement from another market research firm about a new report with flash memory market shares for 2011. I found it remarkable that the way these chips are counted varies enough that the company decided to openly discuss this issue right in the press release for the report!
Memory market statistics are compiled by numerous firms: The World Semiconductor Trade Statistics (WSTS) sold in the US and Europe by the Semiconductor Industry Association (SIA), Gartner Dataquest, IHS iSuppli, Web Feet, Semico, Forward Insights, and even DRAMexchange. Lots of entities use conflicting definitions of what is and what is not a chip. This causes each company’s numbers to differ from the others’.
In the case of WSTS, a chip that is packaged with another chip into a board becomes Continue reading “Figuring Out Who Shipped What”
Tessara’s Invensas subsidiary has announced a new packaging technology to produce what the company calls a “DIMM in a Package.”
The new product is said to deliver the capacity and performance of an SO-DIMM in a 16x16mm BGA. It is built using Invensas’ xFD technology.
I have seen examples of Invensas’ xFD and the first thought that struck me was: “Why didn’t I think of that?!?” It’s an elegantly simple approach to today’s connection conundrums. By staggering chips and mounting them face-down over holes for bonding wires the company connects DRAMs with far shorter interconnect lengths and less scrambling, leading to higher performance.
Although this technology is not yet covered in any of our current reports, we do have a report on cell phone packages: Flash Packaging: What Phone Makers Want and Why, that can be purchased for immediate download on the Objective Analysis website.
MOSAID announced that the company is sampling a 333GB/s 512Gb HLNAND. According to MOSAID the devices packages: “16 industry standard 32Gb NAND Flash die with two HLNAND interface devices to achieve 333MB/s output over a single byte-wide HLNAND interface channel. Conventional NAND Flash MCP designs cannot stack more than four NAND dies without suffering from performance degradation, and would require two or more channels to deliver similar throughput.”
Think of this as a lower-cost NAND version of the Hybrid Memory Cube, which packages specialized DRAM using thousands of through-silicon vias (TSVs) atop a specialized interface. Both approaches use a custom logic chip to quickly move data across a point-to-point interface with the processor.
There were a couple of surprises with this announcement: First that it was made by MOSAID even though the company was acquired by Sterling Partners late last year. It would seem that the announcement would have borne the acquirer’s name.
Second, the press all remarked that the device was innovative since it was a 16-die NAND stack. This is not new! Samsung has been shipping 16-die NAND stacks for a couple of years now. Although it’s not an economical package, it’s in production.
MOSAID first introduced the HLNAND architecture in 2007. The Memory Guy has never fully understood how HLNAND fit in with the rest of MOSAID’s business. For the most part MOSAID has become a licensor and acquirer of IP, a departure from its origins as a chip design consultancy. It is unusual (but not unheard of) for such a company to champion an industry standard and to do much R&D on its own.
Either way, this is an impressive device with compelling throughput. Here’s a wish for MOSAID to successfully create a market for this technology.