Kioxia (formerly Toshiba Memory) has announced another setback to its production: there was a fire on January 7 in the Fab 6 facility of its main Yokkaichi campus.
According to a customer letter that was published by TechNews the fire was limited to a single tool and was rapidly extinguished. Although the news story is in Chinese, a picture of the letter is included, and that letter is in English.
Kioxia seems to be Continue reading “Kioxia Fire. Not Again!”
Readers have asked when I will be speaking at the Flash Memory Summit. There will be a number of opportunities to see me there.
Before I give details, I should make sure that anyone who is unfamiliar with the show knows that this is an annual event that has grown steadily over the past 14 years to become the biggest show of its kind. It is held in the Santa Clara Convention Center in Santa Clara, California, in early August. This year it will be Tuesday-Thursday, August 6-8, and is preceded by the MRAM Developer Day.
Here are the details of Continue reading “My Flash Memory Summit Schedule”
It’s pretty easy to go from talking about the earliest 24-layer 3D NAND to talking about the next-generation 32-layer 3D NAND, and then to progress through 48, 64, and more layers, but the amazing scale of a 96-layer part doesn’t really sink in when you just talk about numbers.
That’s why The Memory Guy was so charmed when Western Digital Corp. (WDC) invited me in for a briefing that gave me a more solid idea of how significant of a number 96 really is. The company brought along a plastic model that replicated the structure of its 96-layer BiCS NAND chip using clear plastic which was dramatically lighted from the inside.
WDC’s model was constructed using standard plastic sheeting, probably 1/8″ thick (~3mm), one sheet to represent the conductive polysilicon and one to represent the insulating silicon dioxide for each layer. Naturally, there are more than 96 layers in 96-layer NAND since there are source select transistors at the bottom and drain select transistors at the top. This adds a little bit to the layer count.
Another layer in the middle of Continue reading “96-Layer NAND in Perspective: WDC Video”
In early February the Samsung Strategy & Innovation Center asked for The Memory Guy to present an outlook for semiconductors as a part of the company’s Samsung Forum series.
Samsung kindly posted a video of this presentation on-line for anyone to watch.
Naturally, the presentation is memory-focused since it consists of the Memory Guy presenting to the world’s leading memory chip supplier. Still, it also covers total semiconductor revenues and demand drivers for future non-memory technologies, as well as memory chips.
During the presentation I explained that the next few years will bring semiconductors into new applications while chips will maintain their strength in existing markets. I showed how semiconductor demand doesn’t change much over time, but that the real swing factor in chip revenues is Continue reading “Video: What’s Driving Tomorrow’s Semiconductors?”
This week the International Solid State Circuits Conference (ISSCC) was held in San Francisco. What was there? The Memory Guy will tell you!
There were three NAND flash papers, one each from Toshiba, Samsung, and Western Digital Corp. (WDC).
Toshiba described a 96-layer QLC 1.33 terabit chip. Like the chip that Toshiba presented last year, this one uses CUA, which Toshiba calls “Circuit Under Array” although Micron, who originated the technology, says that CUA stands for “CMOS Under Array.” Toshiba improved the margins between the cells by extending the gate threshold ranges below zero, a move that forced them to re-think the sense amplifiers. They also implemented a newer, faster, lower-error way to Continue reading “Memory Sightings at ISSCC”
For more than a year The Memory Guy has been fielding questions about Micron’s QuantX products.
First announced at the 2016 Flash Memory Summit, this brand name has been assigned to Micron SSDs and DIMMs that use the Intel/Micron 3D XPoint Memory. Originally QuantX products were scheduled to ship in 2017, but Micron is currently projecting availability in 2019. My clients wonder why there have been these delays, and why Micron is not more actively marketing this product.
The simple answer is that it doesn’t make financial sense for Micron to ship these products at this time.
Within two weeks of the first announcement of 3D XPoint Memory, at the 2015 Flash Memory Summit, I knew and explained that the technology would take two years or more to reach manufacturing cost parity with DRAM, even though Intel and Micron loudly proclaimed that it was ten times denser than DRAM. This density advantage should eventually allow XPoint manufacturing costs to drop below DRAM costs, but any new technology, and even old technologies that are in low-volume production, suffer a decided scale disadvantage against DRAM, which sells close Continue reading “Where is Micron’s QuantX?”
Why has Intel’s NVM Solutions Group (NSG), the owner of the company’s NAND flash, SSD, and 3D XPoint businesses, been losing money during a time when all other manufacturers are more profitable than they have been in years?
This is a question that certain investors have put to The Memory Guy for the past year or so, and it deserves some explanation.
This post’s graphic compares Intel’s NSG net profit margins to the margins published by other memory companies. (Click on it to see the whole chart.) This isn’t a completely clean comparison since the data for Samsung, SK hynix, and Micron includes DRAM, and recent quarters are missing for Western Digital (SanDisk) and Toshiba since these companies have stopped sharing comparable financials, but it still serves as a relatively clear indication that Intel’s NSG (blue) is losing money while all other companies are quite profitable.
Something seems dreadfully Continue reading “Intel’s Losses Amid Others’ Gains”
What really happens in NAND flash during an MLC, TLC, or QLC write? Although there are lots of websites that explain that multilevel cells store four, or eight, or sixteen different voltage levels on a cell (for MLC, TLC, or QLC), they don’t spell out the process of putting those voltage levels onto the bit cell.
Fortunately, Vic Ye, Manager, NAND Flash Characterization at Yeestor Microelectronics Co., Ltd. in Shenzhen, China presented the programming process in a series of short videos at the Flash Memory Summit last August. The Memory Guy was fortunate enough to attend his presentation. Yeestor is a fabless semiconductor manufacturer that manufactures flash storage controllers for SSDs (PCIe & SATA) and flash cards (SD, UFS, eMMC, etc.)
Mr. Ye later gave me permission to share his videos and these are the foundation of this post. They’re brief (13 seconds to 1:10) so they won’t take much time to review. The videos were a part of his slide presentation titled: A Graphical Journey into 3D NAND Program Operations that can be downloaded from The Flash Memory Summit website by clicking the presentation title above and entering your e-mail address.
A multilevel flash bit cell has Continue reading “Videos Demystify MLC NAND Programming”
It’s earnings call season, and we have heard of a slowing DRAM market and NAND flash price declines from Micron, SK hynix, Intel, and now Samsung. DRAM prices have stopped increasing, and that can be viewed as a precursor to a price decline.
Samsung’s 31 October, 2018 3Q18 earnings call vindicated Objective Analysis‘ forecast for a 2H18 downturn in memories that will take the rest of the semiconductor market with it.
Those familiar with our forecast know that for a few years we have been predicting a downturn in the second half of this year as NAND flash prices fall, followed by a DRAM price collapse. After the DRAM collapse the rest of the semiconductor market will undergo a downturn.
We’ve been calling for this downturn for some time. Dan Hutcheson at VLSI Research has been videotaping our forecast every December for the past Continue reading “Memory Market Falling, as Predicted”
Many readers have probably wondered why NAND flash fabs are so enormous. Although DRAM fabs used to be the largest, running around 60,000 wafers per month, NAND flash fabs now put that number to shame, running anywhere from 100,000-300,000 wafers per month. Why are they so huge?
The reason is that you need to run that many wafers to reach the optimum equipment balance. The equipment must be balanced or some of it will be sitting idle, and with some tools costing $50 million (immersion scanners) you want to minimize their idle time to the smallest possible number. I am sure that this is a tough problem, although I have never had to solve it myself.
The most important reason that so much attention is focused on this is that the cost of the wafer depends on the efficiency of the fab. If you built a $13 billion NAND flash fab that produced 90,000 wafers per month instead of 100,000 wafers per month, then the amount of investment per wafer would be 10% higher. That can make a significant difference to Continue reading “Why are NAND Flash Fabs so Huge?”