SLC to MLC to TLC to QLC to PLC: Diminishing Returns

Chart shows asymptotically diminishing cost reductions achieved by migrating from SLC to MLC to TLC to QLC to PLCFrom time to time The Memory Guy is asked to explain why the NAND flash business doesn’t immediately convert to the next larger number of bits per cell once it becomes available.  Many people tend to think that a significant cost benefit will necessarily result from migrating to the next number of bits.  It surprises these folks to find that the cost advantage of moving from TLC to QLC is only half as great as the benefit of moving from SLC to MLC.

There is a diminishing Continue reading “SLC to MLC to TLC to QLC to PLC: Diminishing Returns”

Putting the Brakes on Added Memory Layers

Close-up of a part of the blog post's main graphicFor some time two sides of the computing community have been at odds.  One side aims to add layers to the memory/storage hierarchy while other side is trying to halt this growth.

This has been embodied by recent attempts to stop using objective nomenclature for cache layers (L1, L2, L3) and moving to more subjective names that aim to limit any attempt to add another new layer.

This is a matter close to my heart, since Continue reading “Putting the Brakes on Added Memory Layers”

Why 3D NAND is Stuck at 40nm

Top-Down look at a 3D NAND column with its concentric rings of materialsI recently was asked how much 3D NAND pitches had shrunk since the technology’s 2013 introduction.  Samsung made a big to-do about using 40nm back in 2015, but the company and its competitors don’t seem to have given an update since then.  Shouldn’t it have gone to smaller processes like 35nm, 25nm, 20nm, etc.?

The Memory Guy’s reply was that it’s nearly impossible Continue reading “Why 3D NAND is Stuck at 40nm”

The Invention of Charge Trap Memory – John Szedon

Cartoon of a 4-layer 3D NAND with word balloons speling out the different partsA significant transition has occurred over the past few years that many people don’t know about: Flash memory has moved almost wholesale from the floating gate bit cells, the process that they had always used before, to charge trap bit cells.

Until 2002 all flash used a floating gate.  That year partners AMD & Fujitsu, who later merged Continue reading “The Invention of Charge Trap Memory – John Szedon”

SK hynix Acquires Intel’s NAND Business

Art Nouveau silhouette of dancing coupleSK hynix and Intel today announced that SK hynix will acquire Intel’s NAND flash business for $9 billion.  SK hynix gets Intel’s business, its manufacturing plant with two fabs in Dalian, China, and all of Intel’s designs and intellectual property.  The Memory Guy thinks this is a pretty good deal all around.

Intel doesn’t do well in Continue reading “SK hynix Acquires Intel’s NAND Business”

Applied Materials Video Dramatizes 3D NAND Manufacture

Visualization of a column of ions etching a holeIn a little 3-minute video released this  week for the SEMICON West conference, Applied Materials dramatizes the 3D NAND manufacturing process by using hailstorms for atomic level deposition (ALD) and lightning bolts for etch, all while explaining that the wafer’s surface reaches temperatures hotter than the surface of the sun.

For those who already understand 3D NAND manufacture it’s an interesting Continue reading “Applied Materials Video Dramatizes 3D NAND Manufacture”

Can YMTC Really Win 8% of 2021’s NAND Flash Market?

Aerial Photo of YMTC's NAND flash fab under constructionA couple of weeks ago NAND flash start-up YMTC announced the production release of its 128-layer 1.33 terabit QLC NAND flash chip.  According to a DigiTimes article about the chip the company plans to claim a share of 8% of the global NAND flash market in 2021.

A number of my clients asked The Memory Guy about this, since YMTC doesn’t yet seem Continue reading “Can YMTC Really Win 8% of 2021’s NAND Flash Market?”

Kioxia Fire. Not Again!

Toshiba's Fab 5 in YokkaichiKioxia (formerly Toshiba Memory) has announced another setback to its production: there was a fire on January 7 in the Fab 6 facility of its main Yokkaichi campus.

According to a customer letter that was published by TechNews the fire was limited to a single tool and was rapidly extinguished.  Although the news story is in Chinese, a picture of the letter is included, and that letter is in English.

Kioxia seems to be Continue reading “Kioxia Fire. Not Again!”

My Flash Memory Summit Schedule

Readers have asked when I will be speaking at the Flash Memory Summit. There will be a number of opportunities to see me there.

Before I give details, I should make sure that  anyone who is unfamiliar with the show knows that this is an annual event that has  grown steadily over the past 14 years to become the biggest show of its kind.  It is held in the Santa Clara Convention Center in Santa Clara, California, in early August.  This year it will be Tuesday-Thursday, August 6-8, and is preceded by the MRAM Developer Day.

Here are the details of Continue reading “My Flash Memory Summit Schedule”

96-Layer NAND in Perspective: WDC Video

WDC 96-Layer NAND Model with The Memory GuyIt’s pretty easy to go from talking about the earliest 24-layer 3D NAND to talking about the next-generation 32-layer 3D NAND, and then to progress through 48, 64, and more layers, but the amazing scale of a 96-layer part doesn’t really sink in when you just talk about numbers.

That’s why The Memory Guy was so charmed when Western Digital Corp. (WDC) invited me in for a briefing that gave me a more solid idea of how significant of a number 96 really is.  The company brought along a plastic model that replicated the structure of its 96-layer BiCS NAND chip using clear plastic which was dramatically lighted from the inside.

WDC’s model was constructed using standard plastic sheeting, probably 1/8″ thick (~3mm), one sheet to represent the conductive polysilicon and one to represent the insulating silicon dioxide for each layer.  Naturally, there are more than 96 layers in 96-layer NAND since there are source select transistors at the bottom and drain select transistors at the top.  This adds a little bit to the layer count.

Another layer in the middle of Continue reading “96-Layer NAND in Perspective: WDC Video”