A significant transition has occurred over the past few years that many people don’t know about: Flash memory has moved almost wholesale from the floating gate bit cells, the process that they had always used before, to charge trap bit cells.
Until 2002 all flash used a floating gate. That year partners AMD & Fujitsu, who later merged Continue reading “The Invention of Charge Trap Memory – John Szedon”
SK hynix and Intel today announced that SK hynix will acquire Intel’s NAND flash business for $9 billion. SK hynix gets Intel’s business, its manufacturing plant with two fabs in Dalian, China, and all of Intel’s designs and intellectual property. The Memory Guy thinks this is a pretty good deal all around.
Intel doesn’t do well in Continue reading “SK hynix Acquires Intel’s NAND Business”
In a little 3-minute video released this week for the SEMICON West conference, Applied Materials dramatizes the 3D NAND manufacturing process by using hailstorms for atomic level deposition (ALD) and lightning bolts for etch, all while explaining that the wafer’s surface reaches temperatures hotter than the surface of the sun.
For those who already understand 3D NAND manufacture it’s an interesting Continue reading “Applied Materials Video Dramatizes 3D NAND Manufacture”
A couple of weeks ago NAND flash start-up YMTC announced the production release of its 128-layer 1.33 terabit QLC NAND flash chip. According to a DigiTimes article about the chip the company plans to claim a share of 8% of the global NAND flash market in 2021.
A number of my clients asked The Memory Guy about this, since YMTC doesn’t yet seem Continue reading “Can YMTC Really Win 8% of 2021’s NAND Flash Market?”
Kioxia (formerly Toshiba Memory) has announced another setback to its production: there was a fire on January 7 in the Fab 6 facility of its main Yokkaichi campus.
According to a customer letter that was published by TechNews the fire was limited to a single tool and was rapidly extinguished. Although the news story is in Chinese, a picture of the letter is included, and that letter is in English.
Kioxia seems to be Continue reading “Kioxia Fire. Not Again!”
Readers have asked when I will be speaking at the Flash Memory Summit. There will be a number of opportunities to see me there.
Before I give details, I should make sure that anyone who is unfamiliar with the show knows that this is an annual event that has grown steadily over the past 14 years to become the biggest show of its kind. It is held in the Santa Clara Convention Center in Santa Clara, California, in early August. This year it will be Tuesday-Thursday, August 6-8, and is preceded by the MRAM Developer Day.
Here are the details of Continue reading “My Flash Memory Summit Schedule”
It’s pretty easy to go from talking about the earliest 24-layer 3D NAND to talking about the next-generation 32-layer 3D NAND, and then to progress through 48, 64, and more layers, but the amazing scale of a 96-layer part doesn’t really sink in when you just talk about numbers.
That’s why The Memory Guy was so charmed when Western Digital Corp. (WDC) invited me in for a briefing that gave me a more solid idea of how significant of a number 96 really is. The company brought along a plastic model that replicated the structure of its 96-layer BiCS NAND chip using clear plastic which was dramatically lighted from the inside.
WDC’s model was constructed using standard plastic sheeting, probably 1/8″ thick (~3mm), one sheet to represent the conductive polysilicon and one to represent the insulating silicon dioxide for each layer. Naturally, there are more than 96 layers in 96-layer NAND since there are source select transistors at the bottom and drain select transistors at the top. This adds a little bit to the layer count.
Another layer in the middle of Continue reading “96-Layer NAND in Perspective: WDC Video”
In early February the Samsung Strategy & Innovation Center asked for The Memory Guy to present an outlook for semiconductors as a part of the company’s Samsung Forum series.
Samsung kindly posted a video of this presentation on-line for anyone to watch.
Naturally, the presentation is memory-focused since it consists of the Memory Guy presenting to the world’s leading memory chip supplier. Still, it also covers total semiconductor revenues and demand drivers for future non-memory technologies, as well as memory chips.
During the presentation I explained that the next few years will bring semiconductors into new applications while chips will maintain their strength in existing markets. I showed how semiconductor demand doesn’t change much over time, but that the real swing factor in chip revenues is Continue reading “Video: What’s Driving Tomorrow’s Semiconductors?”
This week the International Solid State Circuits Conference (ISSCC) was held in San Francisco. What was there? The Memory Guy will tell you!
There were three NAND flash papers, one each from Toshiba, Samsung, and Western Digital Corp. (WDC).
Toshiba described a 96-layer QLC 1.33 terabit chip. Like the chip that Toshiba presented last year, this one uses CUA, which Toshiba calls “Circuit Under Array” although Micron, who originated the technology, says that CUA stands for “CMOS Under Array.” Toshiba improved the margins between the cells by extending the gate threshold ranges below zero, a move that forced them to re-think the sense amplifiers. They also implemented a newer, faster, lower-error way to Continue reading “Memory Sightings at ISSCC”
For more than a year The Memory Guy has been fielding questions about Micron’s QuantX products.
First announced at the 2016 Flash Memory Summit, this brand name has been assigned to Micron SSDs and DIMMs that use the Intel/Micron 3D XPoint Memory. Originally QuantX products were scheduled to ship in 2017, but Micron is currently projecting availability in 2019. My clients wonder why there have been these delays, and why Micron is not more actively marketing this product.
The simple answer is that it doesn’t make financial sense for Micron to ship these products at this time.
Within two weeks of the first announcement of 3D XPoint Memory, at the 2015 Flash Memory Summit, I knew and explained that the technology would take two years or more to reach manufacturing cost parity with DRAM, even though Intel and Micron loudly proclaimed that it was ten times denser than DRAM. This density advantage should eventually allow XPoint manufacturing costs to drop below DRAM costs, but any new technology, and even old technologies that are in low-volume production, suffer a decided scale disadvantage against DRAM, which sells close Continue reading “Where is Micron’s QuantX?”