3D NAND: Benefits of Charge Traps over Floating Gates

Real California Cheese Seal(The following is an update of a post that originally ran on 22 November 2013.  It was republished in 2024 as a part of a series to honor the 3D NAND inventors who have received the 2024 FMS Lifetime Achievement Award.)


A prior post in this series (3D NAND: Making a Vertical String) discussed the difficulties of Continue reading “3D NAND: Benefits of Charge Traps over Floating Gates”

FMS – New Focus and a Heavy AI and CXL presence

Last week’s FMS conference, originally the Flash Memory Summit, but now the Future of Memory and Storage, saw a strong return of the show’s original excitement and attendance, with numerous presentations on key new technologies, largely AI and CXL, and crowds similar to those before the pandemic.  FMS is held in early August every year in Santa Clara, California.

The new name is meant to match the show’s content better than Continue reading “FMS – New Focus and a Heavy AI and CXL presence”

Remembering Simon Sze

I was saddened to hear last week of the death this month of Simon Sze, the co-inventor of the floating gate, which was the basis of EPROM, E²PROM, and nearly all flash memory prior to the advent of 3D NAND, which uses a charge trap instead.

Dr. Sze was not only responsible for the floating gate, but he was a pioneer in Continue reading “Remembering Simon Sze”

Infineon Introduces NOR with an LPDDR Interface

Block diagram of a system superimposed over a ghost view of an auto. The system shows a microcontroller communicating with a SEMPER X1 LPDDR NOR flash chip.Infineon recently introduced a NOR flash chip with an LPDDR interface.  Some clients have asked The Memory Guy: “Why would Infineon have done that?”

After all, LPDDR is mostly used in cell phones, and these boot from the enormous NAND flash that’s already in the phone.  A byte of NAND is a couple of orders of magnitude cheaper than a byte of NOR, so a cell phone’s not going to use this part.

Infineon tells us that their target market is Continue reading “Infineon Introduces NOR with an LPDDR Interface”

Introducing a RAM You Never Heard of – CRAM!

1961 photo of a man and a woman posing in front of a computer of that era.Before there was DRAM (1969, Bob Dennard) or SRAM (1963, Robert H. Norman) there was another little-known random-access memory from computer maker NCR that was known as CRAM.  The Memory Guy only recently learned of this technology thanks to a relative’s visit to the NCR Collection in the Dayton History Museum in Dayton, Ohio.

CRAM, a magnetic technology, was a vital part of the Continue reading “Introducing a RAM You Never Heard of – CRAM!”

The Rarely Seen, But Beautiful Content-Addressable Memory (CAM)

Photo of a D3103 chip from a 1973 Intel advertisementAlthough The Memory Guy spends more time writing about NAND and DRAM than almost anything else, several other memory types ship in high volume that many people have never heard of.  One of these is the Content-Addressable Memory, or CAM.

CAMs are kind of backwards.  In a normal memory chip you input Continue reading “The Rarely Seen, But Beautiful Content-Addressable Memory (CAM)”

Introducing New Objective Analysis Briefs

Five briefs on top of each otherAlthough Objective Analysis has published its “Brief” format white papers for some time, this line has never received the focus that it deserves.  To remedy that, we are taking the most interesting and timeless of the Insights that we have published on membership website Smartkarma and providing them to our friends for a reasonable price.

The Brief is a very short report format used to make a succinct Continue reading “Introducing New Objective Analysis Briefs”

Putting the Brakes on Added Memory Layers

Close-up of a part of the blog post's main graphicFor some time two sides of the computing community have been at odds.  One side aims to add layers to the memory/storage hierarchy while other side is trying to halt this growth.

This has been embodied by recent attempts to stop using objective nomenclature for cache layers (L1, L2, L3) and moving to more subjective names that aim to limit any attempt to add another new layer.

This is a matter close to my heart, since Continue reading “Putting the Brakes on Added Memory Layers”

Microchip’s Answer to Emerging Memories

Press Photo of two 8-pin mini-DIPs with Microchip logoMicrochip Technology is now shipping a memory chip that has been designed to provide the most popular features of emerging memory chips without using any non-standard semiconductor technologies.  It’s as fast as an SRAM with the nonvolatility of an EEPROM.

Readers may recall that Tom Coughlin and I recently updated Continue reading “Microchip’s Answer to Emerging Memories”

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