For some time two sides of the computing community have been at odds. One side aims to add layers to the memory/storage hierarchy while other side is trying to halt this growth.
This has been embodied by recent attempts to stop using objective nomenclature for cache layers (L1, L2, L3) and moving to more subjective names that aim to limit any attempt to add another new layer.
This is a matter close to my heart, since Continue reading “Putting the Brakes on Added Memory Layers”
Microchip Technology is now shipping a memory chip that has been designed to provide the most popular features of emerging memory chips without using any non-standard semiconductor technologies. It’s as fast as an SRAM with the nonvolatility of an EEPROM.
Readers may recall that Tom Coughlin and I recently updated Continue reading “Microchip’s Answer to Emerging Memories”
A significant transition has occurred over the past few years that many people don’t know about: Flash memory has moved almost wholesale from the floating gate bit cells, the process that they had always used before, to charge trap bit cells.
Until 2002 all flash used a floating gate. That year partners AMD & Fujitsu, who later merged Continue reading “The Invention of Charge Trap Memory – John Szedon”
During Intel’s latest earnings announcement the company provided information to indicate that 3D XPoint, which Intel sells under the name “Optane”, may have finally reached break-even: It may no longer be selling at a loss.
How would The Memory Guy know? Well, in fact, I don’t, but I can make an informed guess.
The chart below shows Continue reading “Did 3D XPoint Costs Reach Break-Even?”
Readers have asked when I will be speaking at the Flash Memory Summit. There will be a number of opportunities to see me there.
Before I give details, I should make sure that anyone who is unfamiliar with the show knows that this is an annual event that has grown steadily over the past 14 years to become the biggest show of its kind. It is held in the Santa Clara Convention Center in Santa Clara, California, in early August. This year it will be Tuesday-Thursday, August 6-8, and is preceded by the MRAM Developer Day.
Here are the details of Continue reading “My Flash Memory Summit Schedule”
The Memory Guy has found that some people get confused about the terminology surrounding flash “Layers” and “Levels,” Sometimes confusing the two, and often misunderstanding what each one means. This post is meant to be a low-level primer to address that confusion.
There are actually three places where such terminology is used: The number of chips in a package, the number of conductor/insulator pairs in 3D NAND, and the number of voltage levels stored on any single bit cell within the chip. I will address them in that order.
CHIP STACKING: Since the 1990s Both NAND and NOR flash chip makers have been stacking chips within a single plastic package. Originally this approach was used to reduce the size of thin flip phones like the Motorola Razr by stacking an SRAM chip on top of NOR flash, but soon afterwards NAND chips began to use the same approach to get incredible storage capacities into a single IC package or eMMC, or into a microSD card format. What began as 2-die stacks became 4, then 8, and now 16 high. This post’s photo illustrates an 8-high stack.
Since the height of a standard plastic package for a chip is smaller than a stack of 16 full-thickness dice the wafers had to be Continue reading “NAND Flash’s Layers of Layers of Layers”
Last year I stumbled upon something on the Internet that I thought would be fun to share. It’s the picture on the left from a 1978 book by Laurence Allman: Memory Design Microcomputers to Mainframes. The picture’s not too clear, but it is a predecessor to a graphic of the memory/storage hierarchy that The Memory Guy often uses to explain how various elements (HDD, SSD, DRAM) fit together.
On the horizontal axis is Access Time, which the storage community calls latency. The vertical axis shows cost per bit. The chart uses a log-log format: both the X and Y axes are in orders of magnitude. This allows a straight line to be drawn through the points that represent the various technologies, and prevent most of the technologies from being squeezed into the bottom left corner of the chart.
What I find fascinating about this graphic is not only the technologies that it includes but also the way that it’s presented. First, let’s talk about the technologies.
At the very top we have RAM: “TTL, ECL, and fast MOS static types.” TTL and ECL, technologies that are seldom Continue reading “Storage/Memory Hierarchy 40 Years Ago”
My colleague Lane Mason found an interesting history of memories blog post that answers the question: ” What did early computers use for fast read/write storage?”
The post in the Hackaday blog, written by Al Williams, covers drum memories, the Williams Tube and its competitor the Selectron (both briefly discussed in my earlier 3D XPoint post), mercury delay lines, dekatrons, core memory (the original Storage Class Memory), plated wire memory, twistor memory, thin-film memory, and bubble memory.
It also links to interesting videos about these devices.
Think of this as a companion piece to the EE Times memory history slideshow I covered in an earlier post. It’s a fun and educational read!
At the IEEE’s International Electron Device Meeting (IEDM) in December a start-up named Zeno Semiconductors introduced a 1-transistor (1T) SRAM. Given that today’s SRAMs generally use between six and eight transistors per bit, this alternative promises to squeeze the same amount of SRAM into a space 1/6th to 1/8th the size of current SRAM designs, leading to significant cost savings.
The device is really a single standard NMOS transistor that behaves as if it were two bipolar transistors connected into something like a flip-flop, although the transistors’ bases are open, rather than cross-coupled to the opposite transistors’ collector, as is done in a standard flip-flop. Click on the post’s graphic above to see the whole diagram of the cell.
The cell is selected by activating the gate, and the bit is set or sensed via the source and drain to provide a differential signal.
This is a decidedly clever departure from standard SRAM configurations, and it reflects a careful observation of the actual Continue reading “A 1T SRAM? Sounds Too Good to be True!”
With Micron & Intel’s July 28 introduction of their new 3D XPoint memory both companies touted that his is the first new memory in a long time, and that the list of prior new memory types is short.
How short is that list? Interestingly, Intel and Micron have different lists. The Micron list, shown in this post’s graphic (click to enlarge), cites seven types: “Ram” (showing a vacuum tube), PROM, SRAM, DRAM, EPROM, NOR flash, and NAND flash. Intel’s list adds magnetic bubble memory, making it eight. (Definitions of these names appear in another Memory Guy blog post.)
The Memory Guy finds both lists puzzling in that they left out a number of important technologies.
For example, why did Intel neglect EEPROM, which is still in widespread use? EEPROMs (or E²PROMs) are not only found in nearly every application that has a serial number (ranging from WiFi routers to credit cards), requires calibration (like blood glucose monitoring strips and printer ink cartridges), or provides operating parameters (i.e. the serial presence detect – SPD – in DRAM DIMMs), but they still ship in the billions of units every year. In its time EEPROM was an important breakthrough. Over the years EEPROM has had a much greater impact than has PROM.
And, given that both companies were willing to include tubes, a non-semiconductor technology, why did both Continue reading “How Many Kinds of Memory Are There?”