For some time two sides of the computing community have been at odds. One side aims to add layers to the memory/storage hierarchy while other side is trying to halt this growth.
This has been embodied by recent attempts to stop using objective nomenclature for cache layers (L1, L2, L3) and moving to more subjective names that aim to limit any attempt to add another new layer.
This is a matter close to my heart, since Continue reading “Putting the Brakes on Added Memory Layers”
A significant transition has occurred over the past few years that many people don’t know about: Flash memory has moved almost wholesale from the floating gate bit cells, the process that they had always used before, to charge trap bit cells.
Until 2002 all flash used a floating gate. That year partners AMD & Fujitsu, who later merged Continue reading “The Invention of Charge Trap Memory – John Szedon”
Readers have asked when I will be speaking at the Flash Memory Summit. There will be a number of opportunities to see me there.
Before I give details, I should make sure that anyone who is unfamiliar with the show knows that this is an annual event that has grown steadily over the past 14 years to become the biggest show of its kind. It is held in the Santa Clara Convention Center in Santa Clara, California, in early August. This year it will be Tuesday-Thursday, August 6-8, and is preceded by the MRAM Developer Day.
Here are the details of Continue reading “My Flash Memory Summit Schedule”
The Memory Guy has found that some people get confused about the terminology surrounding flash “Layers” and “Levels,” Sometimes confusing the two, and often misunderstanding what each one means. This post is meant to be a low-level primer to address that confusion.
There are actually three places where such terminology is used: The number of chips in a package, the number of conductor/insulator pairs in 3D NAND, and the number of voltage levels stored on any single bit cell within the chip. I will address them in that order.
CHIP STACKING: Since the 1990s Both NAND and NOR flash chip makers have been stacking chips within a single plastic package. Originally this approach was used to reduce the size of thin flip phones like the Motorola Razr by stacking an SRAM chip on top of NOR flash, but soon afterwards NAND chips began to use the same approach to get incredible storage capacities into a single IC package or eMMC, or into a microSD card format. What began as 2-die stacks became 4, then 8, and now 16 high. This post’s photo illustrates an 8-high stack.
Since the height of a standard plastic package for a chip is smaller than a stack of 16 full-thickness dice the wafers had to be Continue reading “NAND Flash’s Layers of Layers of Layers”
With Micron & Intel’s July 28 introduction of their new 3D XPoint memory both companies touted that his is the first new memory in a long time, and that the list of prior new memory types is short.
How short is that list? Interestingly, Intel and Micron have different lists. The Micron list, shown in this post’s graphic (click to enlarge), cites seven types: “Ram” (showing a vacuum tube), PROM, SRAM, DRAM, EPROM, NOR flash, and NAND flash. Intel’s list adds magnetic bubble memory, making it eight. (Definitions of these names appear in another Memory Guy blog post.)
The Memory Guy finds both lists puzzling in that they left out a number of important technologies.
For example, why did Intel neglect EEPROM, which is still in widespread use? EEPROMs (or E²PROMs) are not only found in nearly every application that has a serial number (ranging from WiFi routers to credit cards), requires calibration (like blood glucose monitoring strips and printer ink cartridges), or provides operating parameters (i.e. the serial presence detect – SPD – in DRAM DIMMs), but they still ship in the billions of units every year. In its time EEPROM was an important breakthrough. Over the years EEPROM has had a much greater impact than has PROM.
And, given that both companies were willing to include tubes, a non-semiconductor technology, why did both Continue reading “How Many Kinds of Memory Are There?”
Today Avalanche Technology announced that it is sampling MRAM, making it the world’s second company to actually produce this much-researched technology.
For those unfamiliar with MRAM, it is one of a number of technologies being positioned to replace currently-entrenched memory technologies once they reach their scaling limits. Regular Memory Guy readers know that this juncture has been anticipated for a few decades, but always seems to get postponed.
MRAM, like many other alternative technologies, offers the promise of scaling beyond the limits of DRAM and NAND to become cheaper than ether of these technologies. Add to this its fast write speed, low power, lack of refresh, nearly unlimited endurance, and nonvolatility, and it becomes a very compelling alternative over the long term.
As opposed to the other MRAM-maker Everspin, Avalanche’s MRAM uses Continue reading “Avalanche Samples MRAM”
(Excerpted from an Objective Analysis Alert issued 1 December 2014.)
In a move touted as a merger of equals, Cypress will acquire Spansion in an all-stock transaction slated to close in the second quarter of 2015. The purchase price is estimated at $1.6 billion.
Cypress points out that it is the leading producer of SRAMs, and that Spansion is the leading NOR flash provider.
One striking feature of this transaction is the Continue reading “Cypress to Merge with Spansion”
Some time ago The Memory Guy was asked by Numonyx (later acquired by Micron) to put together an online course for EE Times on memory technologies, explaining how each one works and where it is used.
Although the course was very well received, I never posted a link to it on The Memory Guy blog. This post is intended to correct that error.
The course runs 75 minutes and covers the basics of DRAM, non-volatile RAM, SRAM, NAND flash, NOR flash, mask ROM, and EEPROM. It explains each technology’s advances in size, cost and performance, leading up to the development of Continue reading “Fundamentals of Memory – Free Online Course”
One of the more fun aspects of last week’s Flash Memory Summit was the presentation of the Lifetime Achievement Award. This is something that the show’s management has allowed me to do for the past four events.
This year’s award went to Dr. Simon Sze, who co-invented the floating gate transistor (the basis for all flash, EEPROM, and EPROM) at Bell Labs back in 1967.
Sze and his partner Dawon Kahng were finishing lunch in the company cafeteria with a cheesecake dessert. The two discussed what would happen if a MOSFET was built with extra layers like the layers in the cake. Their intent was to use semiconductors to replace Continue reading “Cheesecake and Floating Gates”
Spansion recently introduced a NOR flash that the company boasts is the: “World’s fastest NOR flash memory”. Named HyperFlash, the chip taps into high-speed SPI interface, doubling its width and adding a differential clock to run at an I/O rates as high as 333MB/s.
In this post’s graphic (click to enlarge) Spansion compares the HyperFlash chip’s sustained read rate (right-hand column) to that of (from left to right) asynchronous parallel NOR, single-bit SPI, industry-standard DDR Quad SPI, and Spansion’s faster rendition of DDR Quad SPI, which Spansion tells us, until now, has been the fastest flash on the market. The company points out that HyperFlash is five times the speed of industry-standard Continue reading “Spansion’s Super-Fast HyperFlash NOR”